Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!samsung!uunet!virtech!cpcahil
From: cpcahil@virtech.uucp (Conor P. Cahill)
Newsgroups: comp.unix.sysv386
Subject: Re: Son of FAS?
Message-ID: <1991Apr25.122805.1708@virtech.uucp>
Date: 25 Apr 91 12:28:05 GMT
References: <1991Apr25.010758.1522@pegasus.com>
Organization: Virtual Technologies Inc.
Lines: 28

richard@pegasus.com (Richard Foulk) writes:

>My question is: couldn't this same technique be used to good advantage
>with the fifo-ized dumb serial cards?

There are several problems with polling.

The first problem is that the fifo's probably aren't big enough to handle 
polling.  Polling is limited to 1 query every kernel clock cycle which
is normally 100 (HZ) in the sysv386 world.  If you are recieving data
at 38.4k (or approx 4,000 bytes per second) you would need at least a
fifo of 40 bytes.  Of course to handle other timing considerations (like
scheduling) the buffer would have to be even larger.

Another problem is that unless the port could be configured with
some form of intelligence, the response to various events (drop of 
cts, XOFF, etc) would be delayed.

>Since most smart cards gain mostly from the reduced interrupt load they
>place on the system wouldn't this blur the difference a bit more?

They can only do this cleanly when they have both fifo space and intelligence
on the cards.

-- 
Conor P. Cahill            (703)430-9247        Virtual Technologies, Inc.
uunet!virtech!cpcahil                           46030 Manekin Plaza, Suite 160
                                                Sterling, VA 22170