Xref: utzoo comp.sys.misc:3335 sci.engr:1051 sci.electronics:19558
Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!think.com!eplunix!raoul
From: raoul@eplunix.UUCP (Nico Garcia)
Newsgroups: comp.sys.misc,sci.engr,sci.electronics
Subject: Re: 74LS is too slow. Maybe?
Keywords: 74LS TTL Logic Computer Design Timing
Message-ID: <1067@eplunix.UUCP>
Date: 23 Apr 91 21:46:13 GMT
References: <1991Apr23.013116.3769@nntp-server.caltech.edu>
Organization: Eaton-Peabody Lab, Boston, MA
Lines: 15

In article <1991Apr23.013116.3769@nntp-server.caltech.edu>, josephc@nntp-server.caltech.edu (Simplelogic (Joseph)) writes:
> My problem is that a couple of 74LS gates will already add up to about 40ns
> to the access time...  Ergo, wait states - something that I don't want
> to have if I can get away without it.

Hmmm. I don't know how the clever digital people did it, but what's
the net delay on a PAL down to these days? Also, can you cleverly
run your gates off the previous clock cycle or the latter half of
it? It's a bit of a kludge, but it might work....


-- 
			Nico Garcia
			Designs by Geniuses for use by Idiots
			eplunix!cirl!raoul@eddie.mit.edu