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From: oasis@gary.watson.ibm.com (GA.Hoffman)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991Apr29.131821.15800@watson.ibm.com>
Date: 29 Apr 91 13:18:21 GMT
References: <1991Apr22.044553.16805@mp.cs.niu.edu> <1991Apr26.073829.4625@kithrup.COM> <TH_A6-F@xds13.ferranti.com> <1991Apr27.162202.18043@ux1.cso.uiuc.edu>
Sender: @watson.ibm.com
Reply-To: oasis@gary.watson.ibm.com (GA.Hoffman)
Organization: IBM T.J. Watson Research Center
Lines: 12

Currently marketed machines have the memory data directly attached to
the processor's cache chips... interleaving was necessary for us to
get acceptable transfer rates for cache lines.  If we could not get
a transfer per cycle we would have to use unacceptably expensive DRAM
for memory.  Our caches are multi-ported... since we build our own
custom VLSI it is cost-effective for us to obtain multi-ported memories
in this fashion. 
-- 
g

gary a hoffman
RISC Systems, Watson Research