Newsgroups: comp.arch
Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!uupsi!ficc!peter
From: peter@ficc.ferranti.com (peter da silva)
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <8W+AYTD@xds13.ferranti.com>
Organization: Ferranti International Controls Corporation
References: <1991Apr22.044553.16805@mp.cs.niu.edu> <1991Apr27.162202.18043@ux1.cso.uiuc.edu>
Date: Mon, 29 Apr 91 15:01:49 GMT

In article <1991Apr27.162202.18043@ux1.cso.uiuc.edu>, shair@ux1.cso.uiuc.edu (Bob Shair) writes:
> The IBM RISC 6000 (models 530 and above) has two-way memory 
> interleaving, allowing two 64-bit words to be loaded or stored
> concurrently (but only to adjacent locations, I belive).

> Is this a first step in this direction?                        

Yes, but a very small one. This sounds like a special case of burst mode
writes. How do they do it, put data on the address bus, or do they have 128
bits of data bus coming into the chip?

To make this really effective you need to have multiple address and
data busses.

(I've been informed that the ETA-10 in fact does this very thing, but
it's pretty much unknown in microprocessors)
-- 
Peter da Silva.  `-_-'  peter@ferranti.com
+1 713 274 5180.  'U`  "Have you hugged your wolf today?"