Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!wuarchive!ukma!vlsi!ulkyvx.bitnet!rmbult01
From: rmbult01@ulkyvx.bitnet (Robert M. Bultman)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991Apr30.073852.253@ulkyvx.bitnet>
Date: 30 Apr 91 11:38:52 GMT
Organization: University of Louisville
Lines: 19

> From: mccalpin@perelandra.cms.udel.edu (John D. McCalpin)
> 
> 	1. multiple functional units	(separate FP add and multiply)
> 	2. pipelined functional units	(independent stages for FP ops)
> 	3. multi-word xfr from cache/(vector registers) to FPU
> 	4. multi-word xfr from main memory to cache/(vector registers)/(fpu)
> 

Sounds like a Multiflow Trace.  4 simultaneous 64-bit FP reads
from memory over 4 data busses to 4 modules, each containing 2
FPUs (separate add and multiply), 2 IUs, 64 sp/32 dp FP
registers, 64 32-bit integer registers, instruction cache only. 
Memory consisted of up to 8 memory controllers with up to 8 banks
of memory per controller, with a 7 beat latency in returning
data.

Rob Bultman
Speed Scientific School
University of Louisville