Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!spool.mu.edu!uunet!crdgw1!crdos1!davidsen From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) Newsgroups: comp.arch Subject: Re: Will NeXT survive? Grow with the times? Message-ID: <3397@crdos1.crd.ge.COM> Date: 30 Apr 91 13:50:43 GMT References: <11399@uwm.edu> <1991Apr29.144421.19819@oakhill.sps.mot.com> <+=+A+N6@xds13.ferranti.com> Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen) Organization: GE Corp R&D Center, Schenectady NY Lines: 21 In article <+=+A+N6@xds13.ferranti.com> peter@ficc.ferranti.com (peter da silva) writes: | Neither the Intel nor Motorola CISC chips show any sign of regaining the | performance edge from RISC, and it's only the existing base of 68000 and | 8086 commodity PCs that has kept the system cost of 680x0 and 80x86 below | the RISC chips. Perhaps integrating the cache, MMU, and FPU on the same chip has had some effect? A savings which I see is now being copied in RISC. Chips like the Intel 32 bit CISC offerings do make design a lot easier, and because of fewer support ships and connection smaller, cheaper, and more reliable. Not that I deny the ecconomies of scale, but there are technical advantages, too. And competition has driven the price down a lot, something we are seeing in the SPARC world. Multiple sources usually bring the price down. -- bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen) "Most of the VAX instructions are in microcode, but halt and no-op are in hardware for efficiency"