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From: prener@watson.ibm.com (Dan Prener)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991Apr30.230958.8556@watson.ibm.com>
Date: 30 Apr 91 23:09:58 GMT
References: <1991Apr22.044553.16805@mp.cs.niu.edu> <1991Apr27.162202.18043@ux1.cso.uiuc.edu> <8W+AYTD@xds13.ferranti.com>
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In article <8W+AYTD@xds13.ferranti.com>, peter@ficc.ferranti.com (peter da silva) writes:
|> In article <1991Apr27.162202.18043@ux1.cso.uiuc.edu>, shair@ux1.cso.uiuc.edu (Bob Shair) writes:
|> > The IBM RISC 6000 (models 530 and above) has two-way memory 
|> > interleaving, allowing two 64-bit words to be loaded or stored
|> > concurrently (but only to adjacent locations, I belive).
|> 
|> > Is this a first step in this direction?                        
|> 
|> Yes, but a very small one. This sounds like a special case of burst mode
|> writes. How do they do it, put data on the address bus, or do they have 128
|> bits of data bus coming into the chip?

There are 128 bits of data bus coming from memory to the cache.
-- 
                                   Dan Prener (prener @ watson.ibm.com)