Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!think.com!paperboy!hsdndev!spdcc!iecc!johnl
From: johnl@iecc.cambridge.ma.us (John R. Levine)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991May02.195346.13664@iecc.cambridge.ma.us>
Date: 2 May 91 19:53:46 GMT
References: <11412@mentor.cc.purdue.edu> <3423@charon.cwi.nl> <1991May2.015410.1470@news.arc.nasa.gov>
Organization: I.E.C.C.
Lines: 17

In article <1991May2.015410.1470@news.arc.nasa.gov> lamaster@pioneer.arc.nasa.gov (Hugh LaMaster) writes:
>PROPHECY:  One of these days, a single-chip microprocessor will have vector
>instructions, and then the advantages and disadvantages of various
>architectural decisions will be discovered all over again.

Perhaps, but I expect we'll be seeing more of the kind of stuff that the
Intel 860 has -- instructions that expose the pipeline so that either a
sufficiently smart compiler or more likely some suitable intrinsics can
synthesize vector ops.  So long as it keep all the execution units busy,
it hardly matters whether it's one instruction or many.  Then again, the
860 certainly has provoked a lot of discussion about its architectural
decisions.

-- 
John R. Levine, IECC, POB 349, Cambridge MA 02238, +1 617 492 3869
johnl@iecc.cambridge.ma.us, {ima|spdcc|world}!iecc!johnl
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