Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!bu.edu!encore!jcallen
From: jcallen@Encore.COM (Jerry Callen)
Newsgroups: comp.arch
Subject: New Moto chips (was Will NeXT survive?)
Message-ID: <14720@encore.Encore.COM>
Date: 3 May 91 15:22:55 GMT
References: <11399@uwm.edu> <JH_ABJF@xds13.ferranti.com> <1991Apr29.144421.19819@oakhill.sps.mot.com> <+=+A+N6@xds13.ferranti.com> <3397@crdos1.crd.ge.COM>
Reply-To: jcallen@encore.Com (Jerry Callen)
Organization: Encore Computer Corp, Marlboro, MA
Lines: 17

In article <3397@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes:
>  Perhaps integrating the cache, MMU, and FPU on the same chip has had
>some effect? A savings which I see is now being copied in RISC. Chips
>like the Intel 32 bit CISC offerings do make design a lot easier, and
>because of fewer support ships and connection smaller, cheaper, and more
>reliable.

Harumph...the latest chip announcements from Motorola include (more or less):

- a 68040 with the MMU and FPU disabled
- a 68030 with the MMU disabled
- cheaper/faster/better 68020s and 68000s (no FPU or MMU to disable)

What's the price of the cheapest Moto chip to include an MMU (68030)?

-- Jerry Callen
   jcallen@encore.com