Newsgroups: comp.lang.c++
Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!think.com!barmar
From: barmar@think.com (Barry Margolin)
Subject: Re: 64 bit architectures and C/C++
Message-ID: <1991Apr29.163448.22381@Think.COM>
Sender: news@Think.COM
Organization: Thinking Machines Corporation, Cambridge MA, USA
References: <168@shasta.Stanford.EDU> <224@tdatirv.UUCP> <295@dumbcat.sf.ca.us>
Date: Mon, 29 Apr 91 16:34:48 GMT

In article <295@dumbcat.sf.ca.us> marc@dumbcat.sf.ca.us (Marco S Hyman) writes:
>In article <224@tdatirv.UUCP> sarima@tdatirv.UUCP (Stanley Friesen) writes:
> > Any one of the above may be the most appropriate depending on the
> > instruction set.  If there are no instructions for 16 bit quantities
> > then using 16 bit short's is a big loss.
>
>Hmmm.  How would such a processor communicate with hardware devices requiring
>16-bit I/O?  How would a structure that maps an external device's registers be
>coded if the registers are 16-bits wide?  If there is a way to do these things
>then a 16-bit wide data type is probably necessary.

You could map each register into the bottom (or top, or middle, or
whatever) 16 bits of adjacent memory words or half-words.

Or, if you want to be really perverse, you make every fourth bit in the
word map into a bit in the register. :{)

--
Barry Margolin, Thinking Machines Corp.

barmar@think.com
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