Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!bu.edu!inmet!rmr
From: rmr@inmet.inmet.com
Newsgroups: comp.lang.vhdl
Subject: Re: Displaying simple schematic circuit
Message-ID: <381900014@inmet>
Date: 1 May 91 13:03:00 GMT
References: <8240@uceng.UC.EDU>
Lines: 11
Nf-ID: #R:uceng.UC.EDU:8240:inmet:381900014:000:393
Nf-From: inmet.inmet.com!rmr    May  1 09:03:00 1991


Valid Logic provides such a capability with their GED Schematic
Capture package.  Your local Valid rep should be able to help you
out with specifics. The Valid capability generates a very
readable structural VHDL description from a GED schematic -- it
was not clear from your mail what direction, GED-to-VHDL or
VHDL-to-GED, you wanted.

Rachael Rusting
Intermetrics, Inc.
rmr@inmet.inmet.com