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From: huck@aspen.IAG.HP.COM (Jerry Huck)
Newsgroups: comp.sys.hp
Subject: Re: HP 7xx : Floating Point Co-Processor (FPC)
Message-ID: <2130011@aspen.IAG.HP.COM>
Date: 30 Apr 91 23:45:10 GMT
References: <1991Apr25.143108.28036@Informatik.TU-Muenchen.DE>
Organization: HP Information Architecture Group - Cupertino, CA
Lines: 20

>In comp.sys.hp, gnatz@Informatik.TU-Muenchen.DE (Rupert Gnatz) writes:
>
>    HP states that  "all arithmetic is performed in compliance with 
>    IEEE standard 754-1985". I would like to know precisely, what levels
>    of that standard are really covered. Is e.g. error handling rigorously
>    implemented?
>
>    Is there a specification available?

Complete compliance to the IEEE/ANSI 754 standard uses a combination
of hardware and software.  Hardware takes care of the basic functions,
rounding, trap handling, and flag settings.  Software must create the
rest of the environment.

The details of the architecture (and hence the required
HW features) is documented in "PA-RISC 1.1 Architecture and
Instruction Set Reference Manual" (HP part number: 09740-90039).

Jerry Huck
Hewlett-Packard