Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!emory!hubcap!johnnyw
From: johnnyw@hubcap.clemson.edu (johnny lee wood)
Newsgroups: comp.sys.m88k
Subject: Data memory unit question?
Keywords: data memory unit
Message-ID: <1991Apr30.002550.9550@hubcap.clemson.edu>
Date: 30 Apr 91 00:25:50 GMT
Organization: Clemson University
Lines: 17


In Motorola's 88000 Family Architecture the data memory unit is said to
have 3 cycles with data transfer to or from cache taking place in the
third cycle.

The user's manual says a store uses the writeback phase to fetch
source data from the register file on the D bus.  These two statements
do not seem to agree.  Again I would appreciate any helpful
explanations.

The last reply concerning Integer Multiply was very helpful.

Also, how is a branch instruction able to know taken or not before
the execute stage.

John Wood
johnnyw@hubcap.clemson.edu