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From: jdp@polstra.UUCP (John Polstra)
Newsgroups: comp.sys.mips
Subject: R2000/3000 Pipeline Questions
Message-ID: <8179@polstra.UUCP>
Date: 25 Apr 91 16:36:21 GMT
Organization: Polstra & Co., Inc., Seattle
Lines: 27

I have a couple of arcane questions about the integer pipeline on the
MIPS R2000 and R3000.

1. In the following sequence of instructions, is register $4 guaranteed
to end up with the value contained in memory location "bbb"?

	lw	$4, aaa
	lw	$4, bbb

2. In the following sequence of instructions, is register $4, guaranteed
to end up containing zero (regardless of what is contained in memory
location "aaa")?

	lw	$4, aaa
	move	$4, $0

I notice in each case that the MIPS assembler does not insert a NOP
after the first load instruction.  Note: these examples will seem less
stupid if you imagine that the first instruction is in the delay slot of
a conditional branch.

Thanks -- enquiring minds want to know . . .
-- 
   John Polstra               polstra!jdp@uunet.uu.net
   Polstra & Co., Inc.           ...!uunet!polstra!jdp
   Seattle, Washington USA              (206) 932-6482
   "Self-knowledge is always bad news."  -- John Barth