Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!think.com!spool.mu.edu!news.cs.indiana.edu!ux1.cso.uiuc.edu!csrd.uiuc.edu!s4.csrd.uiuc.edu!ychen From: ychen@sp1.csrd.uiuc.edu (Yung-Chin Chen) Newsgroups: comp.sys.mips Subject: Re: R2000/3000 Pipeline Questions Message-ID: Date: 2 May 91 23:00:07 GMT Article-I.D.: sp1.YCHEN.91May2180007 References: <8179@polstra.UUCP> Sender: news@csrd.uiuc.edu (news) Organization: /homes/ychen/.organization Lines: 17 In-Reply-To: jdp@polstra.UUCP's message of 25 Apr 91 16:36:21 GMT In article <8179@polstra.UUCP> jdp@polstra.UUCP (John Polstra) writes: > I notice in each case that the MIPS assembler does not insert a NOP > after the first load instruction. Note: these examples will seem less > stupid if you imagine that the first instruction is in the delay slot of > a conditional branch. Don't reply on assembly code (compile with -S option). That is not the real object code. The smart MIPS assembler will re-ordering these codes to eliminate register interlock problems. Your question is only one case of such problems. Only re-ordering failure ( instruction shuffle will result in incorrect execution) will result an extra NOP instruction. That is what I know and I hope it is right. ychen ---------------- UIUC, CSRD