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From: csg@pyramid.pyramid.com (Carl S. Gutekunst)
Newsgroups: comp.sys.misc,sci.engr
Subject: Re: 74LS is too slow. Maybe?
Keywords: 74LS TTL Logic Computer Design Timing
Message-ID: <154005@pyramid.pyramid.com>
Date: 2 May 91 00:21:06 GMT
References: <1991Apr23.013116.3769@nntp-server.caltech.edu>
Organization: Pyramid Technology Corp., Mountain View, CA
Lines: 18

>My problem is that a couple of 74LS gates will already add up to about 40ns
>to the access time...  Ergo, wait states - something that I don't want to
>have if I can get away without it.

Don't mess with F or ALS parts; the rise-times on those parts make for some
difficult noise problems. Plain S will do. Intel and Signetics both make off-
the-shelf birectional and unidirectional buffer chips that should do the job,
with sub 10ns delays. Don't forget to keep your decoding and chip-select paths
real short, too. In some cases you may find that pairs of tri-stated line
buffers wire or'd will be faster than using equivalent birectional parts. (I
think that's actually the way the Intel chips work.) 

I'm not aware of any PALs designed as line buffers; they are normally used for
decoding or state machines. PALs require special equipment to blow their fuses
anyway. (At least, you *want* the special equipment to avoid blowing the chip
instead of the fuses.)

<csg>