Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!samsung!umich!umeecs!msi.umn.edu!cs.umn.edu!uc!noc.MR.NET!gacvx2.gac.edu!gacvx2.gac.edu!scott From: scott@mcs-server.gac.edu (Scott Hess) Newsgroups: comp.sys.next Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: Date: 29 Apr 91 17:31:59 GMT References: <1991Apr10.155032.14786@data.com><1991Apr15.165540.14270@agate.berkeley.edu><1 991Apr22.044553.16805@mp.cs.niu.edu><1991Apr24.170804.25670@kithrup.COM><1991Apr24.181932.17810@cs.cornell.edu> Organization: Gustavus Adolphus College Lines: 35 Nntp-Posting-Host: mcs-server.gac.edu In-reply-to: wayner@CS.Cornell.EDU's message of 24 Apr 91 18:19:32 GMTLines: 35 In article <1991Apr24.181932.17810@cs.cornell.edu> wayner@CS.Cornell.EDU (Peter Wayner) writes: sef@kithrup.COM (Sean Eric Fagan) writes: >Nope, not really. That's the problem: with a "CISC" instruction set, it's >really very difficult to go superscalar, at least compared to some "RISC" >instruction sets. Why? Because not enough registers, too many memory >references in a single instruction, or other small, niggling details. In another sense, going "superscalar" is much easier with CISC machines. I think the Intel 486 does a PUSH instruction in one cycle. In RISC land, this is a decrement and a load. The CISC designer just needs to use enough silicon to pipeline the important instructions. There is no need for complex logic to handle all the possible cases of two instructions coming down the pipe. The RISC designer needs to worry about generality. Not! The CISC instruction set is the one that requires the complex logic to handle all the possible cases. That's because CISC gives you much more to work with. A basic example of the problem is a sequence where the first instruction does a post-increment on one of the registers, and the very next one uses that register. In most RISC machines, this is not possible, as there is no post-increment instruction. Of course, this is not to say that RISC machines don't have data hazards. But, the RISC data hazards are necessarily a subset of CISC hazards, and thus should be _easier_ to handle (I didn't say "easy", I said easier!). Later, -- scott hess scott@gac.edu Independent NeXT Developer GAC Undergrad "Simply press Control-right-Shift while click-dragging the mouse . . ." "I smoke the nose Lucifer . . . Banana, banana."