Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!asuvax!ncar!elroy.jpl.nasa.gov!sdd.hp.com!hplabs!hpda!hpcuhb!hpcuhe!edwardm From: edwardm@hpcuhe.cup.hp.com (Edward McClanahan) Newsgroups: comp.sys.next Subject: Re: Re: RISC vs. CISC -- SPECmarks Message-ID: <32370002@hpcuhe.cup.hp.com> Date: 26 Apr 91 22:11:03 GMT References: Organization: Hewlett Packard, Cupertino Lines: 33 Steven Preston writes: > > I could be wrong, but don't some of the current RISC chips (such as > > IBM's RIOS) begin to approach the complexity of the 68040? > Yes, it is clear that RISC has become a misnomer; it (RISC) now means that > the average cycles per instruction is about 1 or less. > I read somewhere that Motorola claims that the '040 takes an average > of 1.3 clock cycles per instruction. This probably qualifies it as a > RISC machine, by the above criterion. When the "system" is considered (as apart from just the CPU), RISC machines generally have an "average cycles per instruction" greater than one. This is due to things like Cache and Virtual-to-Real Translation Misses. Some "systems" improve their "cpi" by increasing the sizes of their cache(s) and TLBs (caches containing virtual-to-real translations). Here at HP, our RISC processor accesses the Code and Data caches with Virtual Address Tags (as opposed to Physical Address Tags). This allows the Cache and TLB accesses to proceed in parallel instead of serially (i.e. accessing the TLB to get the physical address to index into the Cache). All other things being equal (cache, TLB, memory sizes and access times), just increasing the CPU clock speed actually INCREASES the "cpi". It should be clear that this isn't necessary bad... =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Edward McClanahan Hewlett Packard Company -or- edwardm@cup.hp.com Mail Stop 42UN 11000 Wolfe Road Phone: (480)447-5651 Cupertino, CA 95014 Fax: (408)447-5039