Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!mips!apple!amdcad!dgcad!dg-rtp!webo!cheshirecat!lewine From: lewine@cheshirecat.webo.dg.com (Donald Lewine) Newsgroups: comp.arch Subject: Re: Three Address vs Two Address Architectures Message-ID: <1991May3.142835.9196@webo.dg.com> Date: 3 May 91 14:28:35 GMT References: <22476@shlump.nac.dec.com> Sender: usenet@webo.dg.com (Usenet Administration) Reply-To: uunet!dg!lewine Organization: Data General Corporation Lines: 23 In article <22476@shlump.nac.dec.com>, lan_csse@netrix.nac.dec.com (CSSE LAN Test Account) writes: |> |> What all this boils down to is the question does anybody out |> there have any hard numbers on this? If so, what are they and |> how/where did you get them. If your mail bounces please post |> the information. I will post a summary to the net. Please no |> SWAGs or back of the envelope calculations on this. I can make |> as wild a guess as the next guy. |> When I was a DEC, we did extensive measurements as part of doing the VAX architecture. I don't have the numbers handy (it has been 16 years), however, the answer was: Do both. Assuming that a two address instruction is smaller and faster than a three address instruction, there are a large number of cases where space and cycles can be saved by including both options. -------------------------------------------------------------------- Donald A. Lewine (508) 870-9008 Voice Data General Corporation (508) 366-0750 FAX 4400 Computer Drive. MS D112A Westboro, MA 01580 U.S.A. uucp: uunet!dg!lewine Internet: lewine@cheshirecat.webo.dg.com