Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!cs.utexas.edu!uunet!world!iecc!johnl
From: johnl@iecc.cambridge.ma.us (John R. Levine)
Newsgroups: comp.arch
Subject: Re: Atomic operations (Was Re: Living With Old Baggage)
Keywords: 68040 CAS2
Message-ID: <1991May04.043452.19482@iecc.cambridge.ma.us>
Date: 4 May 91 04:34:52 GMT
References: <14628@encore.Encore.COM> <1991Apr22.175410.9840@decvax.dec.com> <1991May2.201917.15062@dg-rtp.dg.com>
Organization: I.E.C.C.
Lines: 13

In article <1991May2.201917.15062@dg-rtp.dg.com> hamilton@siberia.rtp.dg.com (Eric Hamilton) writes:
>Now I'm curious.  How does one fabricate compare-and-swap out of xmem
>without disabling interrupts?

You can't, at least not without a scheme that uses spin locks which are at
least as bad as disabling interrupts.  See Herlihy's article on "Wait-free
Synchronization" in the January TOPLAS.  It turns out that CAS is
fundamentally more powerful than most other synchronization primitives.

-- 
John R. Levine, IECC, POB 349, Cambridge MA 02238, +1 617 492 3869
johnl@iecc.cambridge.ma.us, {ima|spdcc|world}!iecc!johnl
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