Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!kpc.com!mac From: mac@kpc.com (Mike McNamara) Newsgroups: comp.arch Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <1991May4.225036.16767@kpc.com> Date: 4 May 91 22:50:36 GMT References: <11412@mentor.cc.purdue.edu> <3423@charon.cwi.nl> <1991May2.015410.1470@news.arc.nasa.gov> Organization: Kubota Pacific Computer Incoporated, Santa Clara, CA Lines: 30 In article <1991May2.015410.1470@news.arc.nasa.gov> lamaster@pioneer.arc.nasa.gov (Hugh LaMaster) writes: >The fact that 16 AR's are not enough, is an amusing criticism. True, but >what superscalar machine of today can map 16*64KW*8Bytes/Word = 8 MegaBytes >in its TLB? The ETA-10 had even bigger large pages... The Ardent (now Stardent) Titan P3 maps 256 MBytes in it vector tlb. > >PROPHECY: One of these days, a single-chip microprocessor will have vector >instructions, and then the advantages and disadvantages of various >architectural decisions will be discovered all over again. The tradeoff to be decided is when the 1 million gates of a vector unit aren't better spent on more D cache. I think that once you get 32 K or perhaps 64 K D cache on chip, then it's worth it to spend your next million gates on a vector unit. I think you will see such a chip in 1994. (But then, what do I know?) > > Hugh LaMaster, M/S 233-9, UUCP: ames!lamaster > NASA Ames Research Center Internet: lamaster@ames.arc.nasa.gov > Moffett Field, CA 94035 With Good Mailer: lamaster@george.arc.nasa.gov > Phone: 415/604-6117 #include -- +-----------+-----------------------------------------------------------------+ |mac@kpc.com| Increasing Software complexity lets us sell Mainframes as | | | personal computers. Carry on, X windows/Postscript/emacs/CASE!! | +-----------+-----------------------------------------------------------------+