Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!mips!apple!agate!ucbvax!unisoft!hoptoad!kithrup!sef
From: sef@kithrup.COM (Sean Eric Fagan)
Newsgroups: comp.arch
Subject: Re: skip instructions
Keywords: VLSI, ARCON, RISC, intsructions, SKIP, pipeline
Message-ID: <1991May05.180933.23091@kithrup.COM>
Date: 5 May 91 18:09:33 GMT
References: <1545@geovision.gvc.com> <3446@charon.cwi.nl> <1991May5.162722.29507@berlioz.nsc.com>
Organization: Kithrup Enterprises, Ltd.
Lines: 16

In article <1991May5.162722.29507@berlioz.nsc.com> my@berlioz.nsc.com (Michael Yip) writes:
>The Arcon RISC chip has one (or two??) conditional execution bit in each
>instruction and depends on the condition set by previous instructions

There are four bits in every instruction (the first four, in fact).  If I
could find my ARM manual, I could even tell you what they were 8-(.

I figured out a way, once, to make gcc use them (peepholing, of course).
From the manual, I think I decided that it was really only worthwhile if the
branch would skip over four or fewer instructions.

-- 
Sean Eric Fagan  | "I made the universe, but please don't blame me for it;
sef@kithrup.COM  |  I had a bellyache at the time."
-----------------+           -- The Turtle (Stephen King, _It_)
Any opinions expressed are my own, and generally unpopular with others.