Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!udel!rochester!pt.cs.cmu.edu!o.gp.cs.cmu.edu!spot From: spot@CS.CMU.EDU (Scott Draves) Newsgroups: comp.arch Subject: Re: Three Address vs Two Address Architectures Message-ID: Date: 6 May 91 03:57:53 GMT References: <22476@shlump.nac.dec.com> <1991May3.142835.9196@webo.dg.com> Sender: netnews@cs.cmu.edu (USENET News Group Software) Organization: School of Computer Science, Carnegie Mellon University Lines: 24 In-Reply-To: lewine@cheshirecat.webo.dg.com's message of 3 May 91 14:28:35 GMT In article <1991May3.142835.9196@webo.dg.com> lewine@cheshirecat.webo.dg.com (Donald Lewine) writes: ... the answer was: Do both. Assuming that a two address instruction is smaller and faster than a three address instruction, there are a large number of cases where space and cycles can be saved by including both options. well, on modern machines all instructions are the same size, and doubt very much that using 2-address ops would save you enough that you could increase the clock rate (it certainly won't save you cycle count). As far as i can tell, on a typical RISC machine, the biggest (only?) advantage to 2-address ops is it saves you instruction bits. what if you made a machine with two sorts of every op: one that was 2-address, and one that was 3-address. The two address ones could access only part of the register file. -- christianity is stupid Scott Draves communism is good spot@cs.cmu.edu give up