Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!wuarchive!uunet!munnari.oz.au!brolga!bunyip.cc.uq.oz.au!marlin.jcu.edu.au!csrdh
From: csrdh@marlin.jcu.edu.au (Rowan Hughes)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991May7.061500.7485@marlin.jcu.edu.au>
Date: 7 May 91 06:15:00 GMT
References: <3423@charon.cwi.nl> <11602@mentor.cc.purdue.edu> <1991Apr30.163153.18568@midway.uchicago.edu> <1991May2.162909.9165@news.arc.nasa.gov> <819@cadlab.sublink.ORG>
Organization: James Cook University
Lines: 19

lamaster@pioneer.arc.nasa.gov (Hugh LaMaster) writes:
>	...
>:I have only limited experience with the new, fast-only-in-cache, machines,
>:but I have to say that the code you need to get optimum performance is
>:even more non-intuitive than that for the older vector architecture machines.
>:Even worse, code which was previously optimal for vector machines, and which
>:was OK on a wide variety of other machines, is now pessimal for these machines

I'm a little puzzled by the discussions involving vector vs. risc s-scalar.
Given similar hardware, and an appropriate (vectorizable) algorithm
the vector method should always be much faster. Risc s-scalar machines
are still essentially SISD. Also is a true vector machine using risc
harware likely to emerge soon?
Hope my ignorance isnt too obvious.

-- 
Rowan Hughes                                James Cook University
Marine Modelling Unit                       Townsville, Australia.
Dept. Civil and Systems Engineering         csrdh@marlin.jcu.edu.au