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From: mohta@necom830.cc.titech.ac.jp (Masataka Ohta)
Newsgroups: comp.arch
Subject: Re: ACE (Was Re: Will NeXT survive?  Grow with the times?)
Message-ID: <159@titccy.cc.titech.ac.jp>
Date: 7 May 91 06:03:09 GMT
References: <1991Apr30.191117.4373@vax5.cit.cornell.edu> <32459@usc> <21199@cbmvax.commodore.com> <3005@spim.mips.COM>
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Organization: Tokyo Institute of Technology
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In article <3005@spim.mips.COM> mash@mips.com (John Mashey) writes:

>All current MIPS chips can flip byte order dynamically.  ARC-compliant
>machines (i.e., those able to run shrink-wrapped operating systems
>of ODT and NT) run native little-endian. MIPS, and others, may well
>build machines that can run that, as well as OS variants that support both
>the existing MIPS binaries, and the ODT binaries [this is quite feasible,
>and in fact, not particularly worse than running both BSD and SV and POSIX
>binaries, as we do right now.]

I don't think it so easy.

With the byte order flipping mechanism of R3000, memory, bus and IO is
considered to have the same byte sex with the CPU.

Thus, it is impossible to share memory (of byte stream) between binaries
with different endian. So, shared memory between them is impossible.
Moreover, because buffer cache (and OS in general) must have some byte
sex, there are difficulties in IO with binaries of the opposite byte sex.

Are there any workaround, or dose R4000 have different mechanism for
byte flipping?

							Masataka Ohta