Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!wuarchive!rice!ariel.rice.edu!preston From: preston@ariel.rice.edu (Preston Briggs) Newsgroups: comp.arch Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <1991May7.152921.3307@rice.edu> Date: 7 May 91 15:29:21 GMT References: <1991May2.162909.9165@news.arc.nasa.gov> <819@cadlab.sublink.ORG> <1991May7.061500.7485@marlin.jcu.edu.au> Sender: news@rice.edu (News) Organization: Rice University, Houston Lines: 17 csrdh@marlin.jcu.edu.au (Rowan Hughes) writes: >I'm a little puzzled by the discussions involving vector vs. risc s-scalar. >Given similar hardware, and an appropriate (vectorizable) algorithm >the vector method should always be much faster. I don't see why. Currently it's true, but current vector machines involve a lot more hardware $$ than current superscalars. Superscalars can run vector code fast, plus they can run lots of non-vector code fast. I'd say they superscede vector machines (or will soon). Marty Hopkins made similar comments at ASPLOS recently. So I guess I don't expect to see new vector machines with RISC techniques. Instead, I expect to see superscalars with better compilers. Preston Briggs