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From: gary@chpc.utexas.edu (Gary Smith)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991May7.173125.25412@chpc.utexas.edu>
Date: 7 May 91 17:31:25 GMT
References: <1991May2.162909.9165@news.arc.nasa.gov> <819@cadlab.sublink.ORG> <1991May7.061500.7485@marlin.jcu.edu.au> <1991May7.150724.18806@midway.uchicago.edu>
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In article <1991May7.150724.18806@midway.uchicago.edu>, rtp1@quads.uchicago.edu (raymond thomas pierrehumbert) writes:
|> Rowan Hughes writes:
|> >I'm a little puzzled by the discussions involving vector vs. risc s-scalar.
|> 
|> Vector machines are not really SIMD;  they have parallelization through
|> the pipeline, but the bottom line is that the do not process a whole
|> vector "at once".  The pipeline only means that each pipe spits out
|> a float result each cycle (or two, in the case of a mul-add).  Super
|> scalar machines can also produce a result per cycle.
|> 
|> What I am confused about is why superscalar machines aren't seen as
|> clearly superceding vector architectures.  Like vector architetures,
|> they use instruction overlap to produce a result (or two) per cycle.
|> The difference is that the compiler or the programmer must
|> arrange things so that the proper overlap is possible, whereas with
|> the vector machines you just issue a single vector instruction, i.e.
|> the particular kind of instruction overlap is hard-wired into the
|> silicon (or GaAs).  That would seem to make vector architectures
|> clearly less versatile than superscalar.  Perhaps the restrictions
|> make the hardware easier to build; I imagine they certainly make
|> the compilers easier to write, but progress seems to have been
|> pretty good on RISC compilers. A notable exception is none of 
|> them I have ever seen will automatically do things like strip
|> mining and unroll-and-jam for you.
|> 
|> As far as I can see, insofar as current vector computers have
|> some advantages over superscalar, the performance differences have
|> more to do with memory bandwidth than processor architecture.  I'd
|> be happy to hear other comments on this, though.
|> .
I believe raymond answers his own question (What I am confused
about...) posed in paragraph 2 in the following paragraph (...the
performance differences have to do with memory bandwidth...).

What is the most fundamental reason that organizations are willing
to spend $20+ million for a Y-MP?  I propose the answer is simply
sustainable memory bandwidth of 42.7 gigabytes per second.  Where
are the RISC machines (other than the CRAY) that can provide this?
What would it cost for their designers to provide it?
-- 
Randolph Gary Smith                       Internet: gary@chpc.utexas.edu
Systems Group                             Phonenet: (512) 471-2411
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The University of Texas System                      Austin, Texas 78758-4497