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From: hrubin@pop.stat.purdue.edu (Herman Rubin)
Newsgroups: comp.arch
Subject: Re: Vector vs Cache/Superscalar
Message-ID: <11921@mentor.cc.purdue.edu>
Date: 6 May 91 10:32:31 GMT
References: <1991May4.031835.7979@midway.uchicago.edu> <1991May6.035310.26794@marlin.jcu.edu.au>
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In article <1991May6.035310.26794@marlin.jcu.edu.au>, csrdh@marlin.jcu.edu.au (Rowan Hughes) writes:

			.....................

> The latest Fujitsu compiler (for the VP2000 series) will handle 1st order
> backwards recurrence, ie A(I)=A(I-1)+B(I), as well as the usual forward
> recurrence, in full vector mode. Many old scalar problems can now be
> vectorized. I'd be interested to hear if Cray/ETA/Alliant etc have this
> capability too.

The question is not what the compiler can handle; the older vector machines'
compilers could handle this very well.  The question is what can the vector
hardware handle.  Vector, and other, computers get their speed by allowing
the interval between operations to be short compared to the time for an
operation to complete.

If instructions can issue in one cycle, and the adder is segmented so that
a new addition can start one cycle after one has started, but addition takes
5 cycles (not at all unusual), the cited code can not use the vector
capabilities as written, but can only have an operation every 5 cycles.

Prohibiting the hardware from doing this cannot pay.
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399
Phone: (317)494-6054
hrubin@l.cc.purdue.edu (Internet, bitnet)   {purdue,pur-ee}!l.cc!hrubin(UUCP)