Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!stanford.edu!unix!clipper!gary
From: gary@clipper.ingr.com (Gary Oblock)
Newsgroups: comp.arch
Subject: Clarification on 3 Addr vs 2 Addr Archs
Message-ID: <1991May7.175646.25449@clipper.ingr.com>
Date: 7 May 91 17:56:46 GMT
Organization: Intergraph Advanced Processor Division - Palo Alto, CA
Lines: 41


                 -- My Most Humble Apologies --

I now see that I need to clarify my call for information on 3 address
vs 2 address architectures.

I work for the division of Intergraph that originally developed the
CLIPPER chip set (used in the Intergraph workstations). I'm a
compiler developer and my conversation was with a fellow compiler
developer. The CLIPPER chip set is a load/store architecture with a
small RISCish instruction set. One of the deviations that the CLIPPER
architecture has from the typical RISC architecture is that those
instructions which do arithmetic operations have only two REGISTER
addresses verses the typical three.

This is what I am curious about.  I am not particularly interested in
the `classical' three address architectures such as the PDP-11. What
I'm interested in is one of the characteristics of a `current'
architecture.

----------------------------------------------------------------
end grovel
begin grumble

Come ON guys!

So far only two people have sent me any information. I've also seen
one posting on the subject. I could have sworn that John Mashey would
have something to say about the wisdom of this feature in a RISC
processor. Doesn't anyone like David Wall or John Hennessy (there was
nothing relevant in Hennessy & Patterson) read this group??

 *-------------------------*
 | Gary Oblock             |
 | Intergraph Corp.        |
 | Advanced Processor Div. |
 | 2400 Geng Road          |
 | Palo Alto, CA 94303     |
 | (415)494-8800           |
 | gary@clipper.ingr.com   |
 *-------------------------*