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From: preston@ariel.rice.edu (Preston Briggs)
Newsgroups: comp.arch
Subject: Re: Clarification on 3 Addr vs 2 Addr Archs
Message-ID: <1991May7.195932.8770@rice.edu>
Date: 7 May 91 19:59:32 GMT
References: <1991May7.175646.25449@clipper.ingr.com>
Sender: news@rice.edu (News)
Organization: Rice University, Houston
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gary@clipper.ingr.com (Gary Oblock) writes:

>Come ON guys!
>
>So far only two people have sent me any information. I've also seen
>one posting on the subject. I could have sworn that John Mashey would
>have something to say about the wisdom of this feature in a RISC
>processor. Doesn't anyone like David Wall or John Hennessy (there was
>nothing relevant in Hennessy & Patterson) read this group??

Perhaps no one has done a study, or perhaps people who have are waiting
to publish it somewhere worthwhile, or perhaps they're busy.

I've seen several postings that talked about the trade-offs.
Beyond talk, you need to make some measurements.

It's not too hard to imagine a simple study (give the right tools).
If you've got a 3-address machine, measure a bunch of code.
Then, mark the arithmetic instructions as 2-address
instead of 3-address (pretty dependent on the particular compiler),
and hack the necessary code that tries to take advantage of
2-address instructions.  (Chaitin talks about how to modify
his allocator to handle 2-address instructions).
Then measure the same bunch of code (speed and size).

This won't help you with understanding the benefits of 2-address
instructions (all those extra register addressing bits),
but it will show the costs (extra move instructions).

Then publish the results.

Preston Briggs