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From: jbuck@janus.Berkeley.EDU (Joe Buck)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <42072@ucbvax.BERKELEY.EDU>
Date: 7 May 91 22:16:20 GMT
References: <1991May2.162909.9165@news.arc.nasa.gov> <819@cadlab.sublink.ORG> <1991May7.061500.7485@marlin.jcu.edu.au>
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In article <1991May7.061500.7485@marlin.jcu.edu.au> csrdh@marlin.jcu.edu.au (Rowan Hughes) writes:
>I'm a little puzzled by the discussions involving vector vs. risc s-scalar.
>Given similar hardware, and an appropriate (vectorizable) algorithm
>the vector method should always be much faster. Risc s-scalar machines
>are still essentially SISD. Also is a true vector machine using risc
>harware likely to emerge soon?
>Hope my ignorance isnt too obvious.

The reason that your analysis fails is because of pipelining.  In a
pipelined processor (read: any modern CPU whether RISC or CISC), instruction
fetch of the next instruction overlaps execution of the previous instruction.
As a result, for many RISC machines, if the data are entirely in cache,
the time to do, say, an FP dot product, consists only of the time required
by the multiplier and adder (plus a startup cost).  The time to fetch the
instructions and to fetch the data can be completely overlapped with the
floating point computation.  In addition, there is ususally a separate
instruction cache and data cache, so that the fetching of instructions
happens in parallel with the fetching of data.

On a machine like the RS-6000 there is a separate branch processor, so
even the cost of the branches goes away.  The result of all this is
that there are very few problems where vector machines present any advantages
any more; once your inner loop is in the instruction cache, the cost of
fetching the instruction stream disappears.

--
Joe Buck
jbuck@janus.berkeley.edu	 {uunet,ucbvax}!janus.berkeley.edu!jbuck