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From: csrdh@marlin.jcu.edu.au (Rowan Hughes)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991May8.003919.24525@marlin.jcu.edu.au>
Date: 8 May 91 00:39:19 GMT
References: <1991May2.162909.9165@news.arc.nasa.gov> <819@cadlab.sublink.ORG> <1991May7.061500.7485@marlin.jcu.edu.au> <1991May7.150724.18806@midway.uchicago.edu>
Organization: James Cook University
Lines: 22

In <1991May7.150724.18806@midway.uchicago.edu> rtp1@quads.uchicago.edu (raymond thomas pierrehumbert) writes:
...
>What I am confused about is why superscalar machines aren't seen as
>clearly superceding vector architectures.

I was confused as to why risc is pitted against vector. Surely each
is suited to very different algorithms. I don't see why there're
needs to be some sort comparison.  It would be a better idea
to draw from each others strengths, hence the question about a risc-
vector machine. For current vector machines the bottlenecks are the
scalar unit, and the load/store pipes. Risc machines clearly don't
do so well at vectors (they're "cache busters"). A machine with a
risc style scalar unit and vector arithmetic/memory pipes would have
the best of both worlds. This would give the programmer much greater
flexibility; ie good optimization can be had for both recurrsive
and vector code. It would also take the "mother of all compilers"
to bring it all together.

-- 
Rowan Hughes                                James Cook University
Marine Modelling Unit                       Townsville, Australia.
Dept. Civil and Systems Engineering         csrdh@marlin.jcu.edu.au