Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!think.com!sdd.hp.com!cs.utexas.edu!uunet!mcsun!hp4nl!charon!dik From: dik@cwi.nl (Dik T. Winter) Newsgroups: comp.arch Subject: Re: Anything wrong with the i860 Message-ID: <3487@charon.cwi.nl> Date: 8 May 91 00:00:15 GMT References: <1991May7.145407.18417@midway.uchicago.edu> Sender: news@cwi.nl Organization: CWI, Amsterdam Lines: 12 In article yoshio@maui.cs.ucla.edu (Yoshio Turner) writes: > At the Touchstone special session at DMCC6, I recall one intel speaker > who said the floating point performance suffers from insufficient > memory bandwidth. He also said an updated i860 will be announced in > "a couple months" that addresses this problem. While, indeed, memory bandwidth is a problem, this is not the only problem. I think that lack of registers also play a role. Lack of good compilers play a role. etc. And while we are talking about memory bandwidth, I think the major problem is that at most three loads can be posted concurrently. -- dik t. winter, cwi, amsterdam, nederland dik@cwi.nl