Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!dali.cs.montana.edu!uakari.primate.wisc.edu!sdd.hp.com!wuarchive!uunet!kithrup!sef
From: sef@kithrup.COM (Sean Eric Fagan)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991May08.071855.10486@kithrup.COM>
Date: 8 May 91 07:18:55 GMT
References: <1991May2.162909.9165@news.arc.nasa.gov> <819@cadlab.sublink.ORG> <1991May7.061500.7485@marlin.jcu.edu.au>
Organization: Kithrup Enterprises, Ltd.
Lines: 25

In article <1991May7.061500.7485@marlin.jcu.edu.au> csrdh@marlin.jcu.edu.au (Rowan Hughes) writes:
>I'm a little puzzled by the discussions involving vector vs. risc s-scalar.
>Given similar hardware, and an appropriate (vectorizable) algorithm
>the vector method should always be much faster. Risc s-scalar machines
>are still essentially SISD.

So are the majority of vector machines.  They operate memory-to-memory, and
don't have a seperate functional-unit for each potential element in the
vector.

Also, note that even the Cray is still SISD:  the multiply, recip., and
square root all have to go through the limited number of FU's one at a time
for up to 64 elements in the vector.

As to why the RISC's might be faster:  more registers (does help), better
memory systems (those caches can help, you know), and a quicker design time.

The vector machines, and especially Cray, have an advantage *now*.  Will
they keep it?  Pretty unlikely, I'm afraid...

-- 
Sean Eric Fagan  | "I made the universe, but please don't blame me for it;
sef@kithrup.COM  |  I had a bellyache at the time."
-----------------+           -- The Turtle (Stephen King, _It_)
Any opinions expressed are my own, and generally unpopular with others.