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From: ssr@stokes.Princeton.EDU (Steve S. Roy)
Newsgroups: comp.arch
Subject: Memory speed, why so slow?
Keywords: RAM,cache,memory
Message-ID: <9245@idunno.Princeton.EDU>
Date: 8 May 91 00:58:53 GMT
Sender: news@idunno.Princeton.EDU
Organization: Princeton University
Lines: 32

I have a question for those out there who are in the know about
dynamic RAM.

Is it my imagination or is it true that while the storage capacity of
dynamic RAM chips has increased by orders of magnitude the speed has
not?  Every workstation (or PC for that matter) depends heavily on a
cache of some kind, and for many applications the limiting speed is
not the cpu but the main memory.

Is it a fundamental VLSI level constraint that keeps the cutting edge
memories at a particular speed?  If you consider a chip that has a
given fraction of the storage of a cutting edge chip, will it have a
predictable fraction of the response time?

Is it that the people making chips (driven by the people buying chips)
feel that the current speeds are 'good enough' and the main limitation
is size, and therefore most of the effort goes toward greater density
rather than greater speed?  Do the designers, or whoever makes the
decisions, figure that 'If they really want something faster then
they'll pay for static RAM?'

Just wondering.  This seems to have a bearing on the recent
discussions on memory bandwidth for workstations, mainframes, and
supers.  I certainly find the the current crop of machines is highly
unbalanced in favor of CPU speed and away from memory (or other I/O)
bandwidth.

Steve Roy
ssr@acm.princeton.edu
Program of Applied and Computational Mathematics
Princeton University
Princeton NJ, 08544