Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!samsung!dali.cs.montana.edu!caen!uwm.edu!linac!mp.cs.niu.edu!ux1.cso.uiuc.edu!roundup.crhc.uiuc.edu!roundup.crhc.uiuc.edu!anik From: anik@crhc.uiuc.edu (Sadun Anik) Newsgroups: comp.arch Subject: Re: Vector vs Cache/Superscalar Message-ID: Date: 8 May 91 08:49:33 GMT References: <1991May4.031835.7979@midway.uchicago.edu> <1991May6.035310.26794@marlin.jcu.edu.au> <11921@mentor.cc.purdue.edu> Sender: news@roundup.crhc.uiuc.edu Organization: Center for Reliable and High-Performance Computing Lines: 16 In-Reply-To: glew@pdx007.intel.com's message of 7 May 91 16:53:10 GMT In article glew@pdx007.intel.com (Andy Glew) writes: [ stuff deleted ] So: why not combine vector memory access instructions that convey access pattern, with scalar computational operations? I thought Davidson's SMA architecture could do this. If I remember correctly, a decoupled memory access unit could handle vector access and other data structures. I don't know how much of the original SMA concepts are implemented in ZS1 processor. -- Sadun Anik, U of Illinois at Urbana-Champaign e-mail: anik@crhc.uiuc.edu