Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!convex!krolnik
From: krolnik@convex.com (Adam Krolnik)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Summary: Superscalar is expensive in silicon and time.
Message-ID: <1991May08.230603.20728@convex.com>
Date: 8 May 91 23:06:03 GMT
References: <819@cadlab.sublink.ORG> <1991May7.061500.7485@marlin.jcu.edu.au> <1991May7.152921.3307@rice.edu>
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There are problems that no-one seems to be discussing about implementing 
super-scalar techniques. They all cost a lot of hardware.  Unless you intend 
from the beginning for the architecture have a vliw view, the processor has 
to perform dynamic instruction selection, and issue.  This initial part of
a superscalar processor is very costly in gates and time.  True there are
superscalar boxes out there (HP-PA and RS6000) that are fast.  But the
superscalar techniques made them large. They are not single chip implementations.
And if they were, the gates they consume could be used to increase performance
by allocating them to other functions.  Superscalar gains are a factor of 2-3,
maybe a little larger, but not close to a magnitude. Magnitude gains are achieved by
circuit technology (time) and memory bandwidth.


      Adam Krolnik
      Design Verification  (214)-497-4578
      Convex Computer Corp. Richardson Tx, 75080
	Disclaimer:   What?! Lawyers don't read this stuff do they?