Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!wuarchive!uunet!midway!iitmax!wallace
From: wallace@iitmax.iit.edu (Wallace)
Newsgroups: comp.arch
Subject: Re: ACE (Was Re: Will NeXT survive?  Grow with the times?)
Message-ID: <1991May9.025504.16646@iitmax.iit.edu>
Date: 9 May 91 02:55:04 GMT
References: <21199@cbmvax.commodore.com> <3005@spim.mips.COM> <159@titccy.cc.titech.ac.jp> <3225@spim.mips.COM>
Reply-To: wallace@iitmax.iit.edu (Wallace)
Distribution: comp
Organization: Illinois Institute of Technology
Lines: 27

In article <3225@spim.mips.COM> cprice@mips.com (Charlie Price) writes:
>In article <159@titccy.cc.titech.ac.jp> mohta@necom830.cc.titech.ac.jp (Masataka Ohta) writes:
>>In article <3005@spim.mips.COM> mash@mips.com (John Mashey) writes:
>>
>>>All current MIPS chips can flip byte order dynamically.  ARC-compliant
>If a program is not the native endianess, the OS flips the bytes in
>a word end-for-end on transfers to/from the kernel.
>A non-native text editor can create a text file that the native
>cat program can display.
>
>The cost of doing the data transform for all I/O is not prohibitive.
                                          ^^^^^^^
My kind of guy!
This can be pipelined in the cpu, so, the net cost is one cycle
per flip. Not bad!

Ralph

-- 
=============================================================================
I am not in search of excellence,       
I am in search of perfection.           Dr. Ralph W. Wallace               
                                        
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