Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!uakari.primate.wisc.edu!caen!news.cs.indiana.edu!arizona.edu!arizona!rick From: rick@cs.arizona.edu (Rick Schlichting) Newsgroups: comp.research.japan Subject: Kahaner Report: IPSJ Conf. Proceedings (Book 6), Message-ID: <2938@optima.cs.arizona.edu> Date: 8 May 91 15:46:38 GMT Sender: rick@cs.arizona.edu Lines: 869 Approved: rick@cs.arizona.edu [Dr. David Kahaner is a numerical analyst visiting Japan for two-years under the auspices of the Office of Naval Research-Asia (ONR/Asia). The following is the professional opinion of David Kahaner and in no way has the blessing of the US Government or any agency of it. All information is dated and of limited life time. This disclaimer should be noted on ANY attribution.] [Copies of previous reports written by Kahaner can be obtained from host cs.arizona.edu using anonymous FTP.] From: David K. Kahaner ONR Asia [kahaner@xroads.cc.u-tokyo.ac.jp] Re: Info Proc Soc of Japan, Semi-Annual Meeting, March 12-14, 1991 (Tokyo) 8 May 1991 ABSTRACT. Titles of papers presented at the semi-annual Info Proc Soc of Japan meeting, March 12-14 1991. This report contains the titles and authors in Book 6 of the Proceedings. BOOK 6 (TOPICS) Hardware Parallel Architecture (1) Parallel Inference Machine Parallel Architecture (2) Parallel Processing Computer Architecture (1) (2) Workstation Hardware Description Language/Theory Composition Function/Theory Design Method Circuit/Theory Simulation Theory Design Verification/Fault Diagnosis Layout Design Support Automatic Placement/Routing Commonly-used Computer System Office System CAI User Interface Decentralized System CAD CIM PROCEEDINGS OF 42ND INTERNATIONAL GENERAL MEETING BOOK 6 (TITLES/AUTHORS) HARDWARE Parallel Architecture (1) Message-flow: A New Computation Model for MIMD-type Parallel Machines Hiroaki Fujii, Kiyoshi Shibayama (Kyoto University) On Parallel Architecture for Hard Real-time Applications Kenji Nishida, Shuichi Sakai, Kei Hiraki, Kenji Toda, Yoshinobu Uchibori, Toshio Shimada (Electrotechnical Laboratory) Parallel Computer Architecture for Term Rewriting Systems Jun Kamada (Nagoya University) B-Net of Highly Parallel Processor AP-1000: Architecture & Evaluation Sadayuki Kato, Hiroaki Ishihata, Toshiyuki Shimizu, Takeshi Horie (Fujitsu Laboratories, Ltd.) Past Sharing Data on Tightly Coupled Multiprocessor and its Implementation with Addressing Mode Hiroshi Hoshino, Hiroshi Kitano, Toshihiro Suzuki, Masaki Tomisawa, Satoshi Igarashi, Oichi Atoda, Nobuo Saito (Tokyo University of Agriculture and Technology) Exceptions and Protections Mechanism for Tightly Coupled Multiprocessor Hitoshi Tamura, Masaki Tomisawa, Satoshi Igarashi, Oichi Atoda, Nobuo Saito (Department of Computer Science, Faculty of Technology, Tokyo University of Agriculture and Technology) Simulation for Various Implementation of base-m n-cube Network Yasushi Kawakura, Noboru Tanabe, Takashi Suzuoka (Toshiba Research and Development Center) Simulator for a Parallel Object-oriented Total Architecture A-NET Masahiro Hamada, Tsutomu Yoshinaga, Takanobu Baba (Utsunomiya University) Performance Estimation of the Data Parallel Computing Model by Livermore Loops Eiichiro Maeda (Hitachi Nuclear Engineering Co., Ltd.) Kousuke Sakoda, Hiroshi Ohta (Hitachi Ltd.) Tetsuo Saito, Toshiyuki Yamamoto (Hitachi Microcomputer Engineering Ltd.) Parallel Inference Machine On Scheduling and Load Distribution of the Parallel Processing Management Kernel of PIE64 Yasuo Hidaka, Hampei Koike, Hidehiko Tanaka (Faculty of Engineering, University of Tokyo) Extended Dereference Mechanism for PIE64 Takeshi Shimizu, Hanpei Koike, Hidehiko Tanaka (The University of Tokyo) The Inference Processor UNIRED II: Performance Evaluation Using Simulation Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka (Faculty of Engineering, University of Tokyo) Performance Evaluation of PIM/m Front End Processor Minoru Saeki, Hiroshi Nakashima, Hirokazu Tateno, Morihiro Ikeda, Ryuji Tajima (Mitsubishi Electric Corporation) Garbage Collector of PIM/m Front-end Processor H. Tateno, K. Takahashi, M. Ikeda (Mitsubishi Electric Co., Ltd.) Y. Kawada (SET) KL1 System on the Intercluster Shared Memory Hiroshi Sakai, Akihiko Nakase, Toshiaki Takewaki (Toshiba Corporation) Measurements of Instruction Set Usage of the Processing Element of Parallel Inference Machine PIM/i Koichi Takeda, Masatoshi Sato, Teruhiko Oohara (Oki Electric Industry Co., Ltd.) Evaluation of Tagged Architecture on Parallel Inference Machine PIM/i Kenji Kato, Masatoshi Sato, Koichi Takeda, Teruhiko Oohara (Oki Electric Industry Co, Ltd.) Evaluation of the Parallel Inference Machine PIM/i Memory System - Parallel Cache Teruhiko Oohara, Koichi Takeda (Oki Electric Industry Co., Ltd.) Masaki Sato (ICOT) Branch Behavior in Parallel Inference Machine PIM/i Masatoshi Sato, Koichi Takeda, Teruhiko Oohara (Oki Electric Industry Co., Ltd.) Parallel Inference Machine PIM/c - Development of PIM/c Firmware Takayuki Nakagawa, Machiko Asaie, Mamoru Sugie (Hitachi Ltd.) Shigeru Hayaki (Hitachi Microcomputer System Ltd.) Hiroyuki Imanishi (Human Systems Inc.) Parallel Inference Machine PIMN/c - Automatic Generation of Micro Instruction Address to Make Branch Cost to Zero (Hiroyuki Imanishi, Ryo Sakuma, Jyouichi Ojima (Human Systems Inc.) Shigeru Hayaki (Hitachi Microcomputer System Ltd.) Takayuki Nakagawa, Mamoru Sugie (Hitachi Ltd.) Parallel Architecture (2) Stream Data Processing on Massively Parallel Image Processor AMP Hiroshi Tomiyasu, Noriyasu Yamamoto, Naoyuki Turuta, Rinichiro Taniguchi, Makoto Amamiya (Graduate School of Engineering Science, Kyushu University) Evaluation of Dynamic Function Distributions in the EM-4 Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi (Electrotechnical Laboratory) Adaptive Optimization Methods on the EM-4 Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi (Electrotechnical Laboratory) VLIW Computer KIDOCH with 5 Port Register Files Masato Abe (Computer Center, Tohoku University) Keniti Kido (Chiba Institute of Technology) All-to-all Communication Network Controlled by Local Intelligence Yasuo Noguchi, Riichirou Take, Haruo Yokota (Fujitsu Laboratories Ltd.) A Processor Element LSI for Data Driven Computer "EDDEN" Hiroki Miura, Hideki Ohashi, Masahisa Shimizu (Sanyo Electric Co., Ltd.) Overview of Systolic Array for Image Processing Tetsuo Nakazawa, Makoto Odajima, Atsushi Kawai (Oki Electric Industry Co, Ltd.) A Contention-Free Multiport Frame Buffer for Multicomputer Systems Satoshi Nishimura, Ryo Mukai, Tosiyasu L. Kuni (Department of Information Science, Faculty of Science, The University of Tokyo) An Example of the Cache Prefetch Control for a Tightly Coupled Multi- Processor System Noboru Yamamoto (Faculty of Engineering, Mihon University) Parallel Processing A Parallel Execution Scheme of Conditional Branches and its Evaluation for the Parallel Processing System - Harray Hayato Yamana, Toshiaki Yasue, Jun Kohdate, Yoichi Muraoka (Waseda University) A Control Scheme of Processing Elements for the Parallel Processing System - Harray Kazuaki Ishizaki, Yoshihiko Ishii, Takeshi Hagimoto, Hayato Yamana, Yoichi Muraoka (Waseda University) Optimizing Multiprocessor Scheduling Algorithm Considering Inter- processor Data Transfer Keisuke Itoh, Sho Miyagawa, Hironori Kasahara (Waseda University) Data-reploading and Data-poststoring Algorithm for Hierachial Memory Multiprocessor System Kazunori Fujiwara Hironori Kasawara (Waseda University) Kensuke Shiratori (NTT DATA Communications Systems Corporation) Makoto Suzuki (Mitsubishi Heavy Industries, Ltd.) Performance Evaluation of Static Scheduling Method "CP-DTSP" Resistive to Dynamic Fluctuation of Execution Timing Hiromitsu Takagi, Takaya Arita, Masahiro Sowa (Nagoya Institute of Technology) Nonlinear MHD Plasma Simulator on Cenju Satoshi Matsushita (NEC Corporation) Masaru Narusawa (NEC Scientific Information System Development Ltd.) Genichi Kurita, Toshihide Tsunematsu, Tatsuoki Takeda, Nobuhiko Koike (Japan Atomic Energy Research Institute) Evaluation of Finite Element Analysis on the Parallel Simulation machine Cenju - Parallel Calculation of Stiffness Matrix Yasushi Kanoh, Toshiyuki Nakata, Nobuhiko Koike (C&C Systems Research Laboratories, NEC Corporation Hidehito Okumura, Kunihiko Ohtake, Takashi Nakamura, Masahiro Fukuda (National Aerospace Laboratory) Parallel Processing of Fortran Subroutines on OSCAR Akiyoshi Mogi, Hiroki Honda, Hironori Kasahara (Dept. of Electrical Engineering, Waseda University) A Hierarchical Macro-dataflow Computation of Fortran Program on OSCAR Akio Ogura, Kento Aida, Hiroki Honda, Hironori Kasahara, Seinosuke Narita (Waseda University) A Parallel Processing Scheme for the Cellular Neural Network Simulation on OSCAR Akihiro Yoshioka, Chunchen Lin, Hironori Kasahara, Seinosuke Narita, (Waseda University) L.O. Chua (University of California, Berkeley) A Parallel Processing of the Layered-Neural-Network Learning Calculation on OSCAR Haruhiko Iida, Hideo Wakada, Hironori Kasahara (Waseda University) Keiichi Nakano (Olympus Optical Co., Ltd.) Debugging System for OSCAR Kazufumi Takizawa, Hironori Kasahara, Seinosuke Narita (Waseda University) Computer Architecture (1) The Evaluation of 3-D Integrated Circuit Technology by Studying the Layout of FFT Circuits Yasuhiko Ichijo, Takakazu Kurokawa (Department of Computer Science, The National Defense Academy) A Parallel Processing Suitable to Three Dimentional Circuit Hideo Ohhigashi (Electrotechnical Laboratory) A Trial on Performance Evaluation of Asynchronous Processors Yoichiro Ueno, Narihito Kon, Takashi Nanya (Faculty of Engineering, Tokyo Institute of Technology) Optically Connected Multi-Read/White Memory Takashi Takemoto, Hideharu Amano (Keio University) A Study of an Evaluation Method for Bus Spilit Architecture Kazunori Takahashi, Hiroshi Kamiyama, Masashi Deguchi (Kansai Information and Communications Research laboratory, Matsushita Electric Industrial Co., Ltd.) Hardware Development of the ELIS-VME Board Katsumi Shibuya, Kazuichirou Kodaira (Ohkura Electric Co., Ltd) Tatsuo Suzuki (NTT Intelligent Technology Co., Ltd.) Management for the ELIS-VME Board Kazuichirou KODAIRA, Katsumi Shibuya (Ohkura Electric Co., Ltd.) Tatsuo Suzuki (NTT Intelligent Technology Co., Ltd.) Development of ELIS Board for PC Hiromasa Kawamura (NTT Human Interface Laboratories) Application of the New ELIS LSI Chip to AI Engine Kazufumi Watanabe (NTT Human Interface Laboratories) Computer Architecture (2) Tree-structured General-purpose Pipeline using Transputers Tadayoshi Nakajima, Masaaki Fukase, Tadao Nakamura (Tohoku University) A Note on Fault Tolerance in Multi-layer Neural Networks Yasuo Tan and Takashi Nanya (Faculty of Engineering, Tokyo Institute of Technology) Computer System for Japanese Language Processing Kazuo Kurokawa, Katsumi Osuga (Science University of Tokyo) Architecture of Japanese Language Processing Computer Katsumi Osuga, Toshiyuki Nakagawa, Kenji Ishimatsu, Kazuo Kurokawa (Science University of Tokyo) A Structure of Efficient Control Memories for a Hardware Concurrency Control Hiroki Takakura (Faculty of Engineering, Kyushu University) Yahiko Kambayashi (Facultyu of Engineering, Kyoto University) Design of a Hardware Log Management System to Reduce Logging Overhead Hiroki Takakura, Tomoya Amie (Faculty of Engineering, Kyushu University) Yahiko Kambayashi (Facultyu of Engineering, Kyoto University) Functional Reduction and Restoration Control of Disk Controller Masaharu Akatsu, Tomohiro Murata, Kenzo Kurihara, Shigeo Honma (Hitachi, Ltd.) High Performance Channel Technology of Superminicomputer Tadashi Yoneyama, Junichi Kihara (Toshiba Corp.) Workstation Laptop Workstation SPARC LT System Overview Tsuyoshi Tokoro, Akio Otani, Tadashi Hayashi (Toshiba Corporation Fuchu Works) Laptop Workstation SPARC LT Hardware Architecture Kohki Hasebe, Yoshiaki Bandai, Yoshinobu Sano (Toshiba Corp. Information and Communications Systems Laboratory) Laptop Workstation SPARC LT Imput/Output System Tsuyoshi Igarashi (Toshiba Corp. Information and Communication Systems Laboratory) Takashi Kosaka (Toshiba Corp. Fuchu Works) Laptop Workstation SPARC LT Display System Yutaka Oshima, Koutarou Kuwashima (Toshiba Corp. Information and Communications Systems Laboratory) Masayuki Murakami (Toshiba Corp. Fuchu Works) Laptop Workstation SPARC LT Extension Bus Yoshiyuki Satoh, Nobuhiko Yamagami (Toshiba Corp. Information and Communication Systems Laboratory) Packing Technology of Laptop Workstation SPARC LT Fumiaki Takeda, Toshimasa Murano (Toshiba Corporation Fuchu Works) Laptop Workstation SPARC LT Application Binary Interface Compatibility of OS Hideo Nagai, Yasuichiro Izumi, Tomoaki Murakami, Masayuki Murayama (Toshiba Corp, Fuchu Works) Hardware Description Language/Theory Composition An Extended TS Chart Compiler for VHDL Yoichi Matsuda, Shigeyuki Ohara, Akio Odaka (Tokai University) Development of a UDL/I Simulation System based on Semantics Definition Koji Tankai, Fumitsugu Ohtaka, Hiroto Yasuura, Keikichi Tamaru (Kyoto University) Modifications of the Procedure Generating 3-level Initil Circuits for Transduction Method and its Evaluation Sunao Sawada (Faculty of Engineering, Kyushu University) Yahiko Kambayashi (Faculty of Engineering, Kyoto University) A BDD-based Two Level Minimizer for Multi Level Logic Synthesis Yusuke Matsunaga, Masahiro Fujita (Fujitsu Laboratories, Ltd.) K.C. Chen (Fujitsu America Inc.) An Automatic Method for Exhaustive Verification, Correction and Selection of Logic Circuits Satoshi Wakabayashi, Hiroyuki Ishikawa (Graduate School of Hosei University) Takashi Ichikawa, Ryo Dang (College of Engineering, Hosei University) Latch Reallocation Method for Sequential Networks Noriharu Hiratsuka, Tsuguo Shimizu, Kazumasa Shimada, Keisaku Bekki (Hitachi, Ltd.) A Method for Automatic Synthesis of Control Circuits in Asynchronous Processors Hiroto Kagotani, Hitoshi Doi, Takashi Nanya (Faculty of Engineering, Tokyo Institute of Technology) Hardware Sorter Design by using a High-level DA System A2DL-DA Tetsuya Yamazaki, Ryuichi Takahashi 9NEC Corporation) High-level Synthesis in a Design Automation System A2-DL-DA Yuichi Takahashi (C&C Systems Research Labs, NEC Corporation) Function/Theory Design Method A Functional Design Algorithm for a High-Speed Digital Circuit using Multiphase Clocking Toshinori Hayashi (Computing Center, Hokkaido University) Yuzuru Tanaka (Faculty of Engineering, Hokkaido University) Minimization of Ring-sum Expansions Using Transform Methods Y.X. Shui, K. Shimizu (Gunma University) Asynchronous Master-slave Register for 2-rail 2-phase Data Transfer Yukihito Kawabe, Tokuyasu Katayama, Yoshinori Yamamura, Takashi Nanya (Faculty of Engineering, Tokyo Institute of Technology) A Vector Algorithm for Mainpulating SBDD Hiroyuki Ochi, Nagisa Ichiura, Shuzo Yajima (Kyoto University) Minimum-width Method of Variable Ordering for Shared Binary Decision Diagrams Shinichi minato (NTT LSI Lboratories) A Timing Optimization Method for Logic Synthesis Nobuhiro Takeda, Katsumi Harashima, Junko Yamanouchi, Takashi Kambe (Sharp Corporation) On Delay Assumption for 2-rail 2-phase Data Transfer in Asynchrous Processors Tokuyasu Katayama, Kouji Kawabe, Yoshinori Yamamura, Takashi Nanya (Faculty of Engineering, Tokyo Institute of Technology) An Algorithmic Level LSI Design Including Redesign by Selecting Search Branch based on Evaluation Xing-jian Xu, Mitsuru Ishitsuka (University of Tokyo) Overview of the Application Specific Integrated Processor Design Environment Jun Sato, Tetsuya Hakata, Alaudain Y. Alomary, Masaharu Imai (Department of Information and Computer Sciences, Toyohashi University of Technology) Nobuyuki Hikichi (Software Research Associates) Compiler Generator for the Application Specific Integrated Processor Design Environment Tetsuya Hakata, Jun Sato, Masdaharu Imai (Department of Information and Computer Sciences, Toyohashi University of Technology) Nobuyuki Hikichi (Software Research Associates) Hierchical Design of Microprogrammed-controller Based Sequential Machines Using Algebraic Methods Junji Kitamichi, Kouichi Narahara, Kenichi Taniguchi (Dept. of Information & Computer Science, Osaka University) Circuit/Theory Simulation Interactive Supercomputing of Circuit Analysis in a CRAY Y-MP Hirotoshi Yoshida, Yuko Yoshida (Toshiba Corporation) Masami Abe (Toshiba CAE Systems Inc.) A Multi-level System Simulator for LSI Enhancement Chiaki Hirai, Toshinori Watanabe, Shinichi Hayashi (Hitachi, Ltd.) An Effecient Logic Verification and Trouble Shooting Method using HAL III Kyoko Naritomo, Yoshihiro Hirabayashi, Masahiro Kurashita, Sigeru Takasaki (NEC Corporation) Masaru Nakata (NEC Software Hokuriku, Ltd.) One-chip Simulation Engine: TASSE II W. Tomita, N. Suganuma, S. Tada, K. Hirano (Kobe University) A Method of Speed-up for Vectorized Event-Driven Logic Simulation System Yoshito Mizoue, Yoshiaki Kinoshita, Yoshio Takamine, Masayuki Miyoshi (Hitachi, Ltd.) Yoshiyuki Nagata, Motonobu Nagafuji (Hitachi Computer Engineering Co., Ltd.) Parallel Logic-level Simulation based on the Virtual Time Yukinori Matsumoto, Kazuo Taki (Institute for New Generation Computer Technology) Research on Accelerating Fault Simulation - (1) Excepting Un-observable Faults Mika Kamiwaki, Takaharu Nagumo, Takao Nishida (Central Research Laboratory, Hitachi, Ltd.) Research on Accelerating Fault Simulation - (2) Pre-propagating Faults Before Simulation Takaharu Nagumo, Mika Kamiwaki, Takao Nishida (Central Research Laboratory, Hitachi, Ltd.) Analysis of Timing Error Probability Using Probablistic Coded Time- symbolic Simulation Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima (Kyoto University) A Consideration of Improving Delay Calculation Precision Between LSI and LSI Based on Hierachical Method Reiji Toyoshima, Hidetomo Hongo, Sachie Kawada (Hitachi Computer Engineering Co., Ltd.) Tatsuki Ishii, Seiichi Kawashima, Masakazu Yamamoto (Hitachi, Ltd.) The Effect of Wire Delay in Synchronous Systems Hiroyoshi Itoh, Takashi Nanya (Faculty of Engineering, Tokyo Institute of Technology) Design Verification of MOS Synchronous Circuits Yuji Kukimoto, Tsutomu Saito, Hidehiko Tanaka (Faculty of Engineering, The University of Tokyo) A Method of Logic Verification for Network Equipment Kazunobu Morimoto, Yoshio Sato, Masato Morita, Haruo Nonaka (Hitachi, Ltd.) Masaru Fujino, Kazuo Suzuki (Hitachi Computer Electronics Co., Ltd.) A Logic Verification Coverage for Primitive Functions Hong-Hai Jiang, Tamotsu Yamamoto, Yoshihiro Hayashi (University of Tokyo) Masahiro Tomita (Kobe University) A Consideration About Verification of Isolation for Incircuit Board Diagnosis Tsutomu Tsujimura, Masayo Seto, Hiroyuki Kuroki (Hitachi Ltd.) Kazunori Satoh, Futoshi Kaneta, Kazuo Suzuki (Hitachi Computer Electronics Co., Ltd.) On Functional Information Extraction from Synchronous Sequential Circuits Mashiko Ohmura, Hiroto Yasuura, Keikichi Tamaru (Faculty of Engineering, Kyoto University) Suggestion of Test Pattern Language for ASIC Masanori Ushikubo, Hisashi Hembo, Michio Murakami (Oki Electric Industry Co., Ltd.) The Coincidence Error Detecting Scheme for the Combinational Logic Circuits and its Applications Shigeya Tsuki (Suzuka College of Technology) Takahiro Haga (Aichi Institute of Technology) A Fault Diagnosis and Recovery for a Batcher Sorter Hideharu Amano (Keio University) A Consideration of Test Method for RAM with Logic LSI Kazuhiro Kojima, Shigeo Sayama, Yoshio Hinataze (Hitachi Computer Engineering Co., Ltgd.) Kaoru Moriwaki (Hitachi, Ltd.) An Automatic Multiple Logic Design Errors Location Method Tamotsu Yamamoto, Hong-Hai Jiang, Yoshihiro Hayashi (University of Tokyo) Masahiro Tomita (Kobe University) Layout Design Support Evaluation Report on an Interactive Analog LSI Layout Design System Kazuhito Kondou, Hisashi Sasaki (Toshiba Microelectronics Corp, Toshiba Corp.) A Module Generator for Analog LSI A. Nagao, T. Yamanouchi, M. Otoi, T. Kambe (Sharp Corp.) Physical Design Technique of Clock Logic for VLSI Masahiro Yamada, Kazuo Suzuki, Munehiro Sasagawa, Naoki Furuta (Hitachi Computer Electronics Co., Ltd.) Shun Isiyama, Toshihiro Okabe (Hitachi, Ltd.) A Design Support System for VLSI Chip Peripheral Layout Kazuaki Gotoh, Takashi Koresawa (Oki Micro Design Miyazaki Co., Ltd.) Mitsuru Nadaoka (Oki Electric Industry Co., Ltd.) On-chip Modification Design Automation System for LSI's Katsuyoshi Suzuki, Yoosuke Nagao, Tatsuki Ishii, Yasuo Satou, Masahito Hamamoto (Hitachi Ltd.) Kouji Takahashi, Tomio Taniguchi (Hitachi Software Engineering Co., Ltd.) Routing Pattern Optimizer System for LSI's On-chip Modification Yoshiyuki Kawashima, Masao Ogino (Hitachi Software Engineering Co., Ltd.) Yasuo Satou, Takuji Itoh, Yasuhiro Ikemoto, Katsuyoshi Suzuki (Hitachi Ltd.) On-chip Modification Availability Check System for LSI's Tomio Taniguchi, Naoko Toyoda (Hitachi Software Engineering Co., Ltd.) Yoshihiko Tomoshige (Hitachi Ltd.) On-chip Modification Data Input and Check System for LSI's Tsutomu Nakajima, Kouji Takahashi, Sachip Kikuchi, Yuuichirou Kaida (Hitachi Software Engineering Co., Ltd.) Akiko Yokokawa (Hitachi Ltd.) Module Generator for Custom LSI Designs Tomohiro Yoshizumi (Oki Micro Design Miyazaki Co., Ltd.) Automatic Placement/Routing A Routing Method for Macro Cell VLSI Layout in a Chip Planning System Michiyo Nakatani, Chiyoshi Yoshioka, Shinichi Fujiwara, Tokihito Okada, Takashi Kambe (Sharp Corporation) Macro Cell Placement based on Rectangular Dual Yutaka Tamiya, Masahiro Fujita, Taeko Kakuda, Yusuke Matsunaga (Fujitsu Laboratories, Ltd.) A Placement Algorithm for Sea-of-gates Layouts Mikiko Sode, Masato Edahiro, Takeshi Yoshimura (C&C Systems Research Laboratories, NEC Corporation) Placement Argorithm for CMOS Free Channel Gate Array Hirotake Tokuyama, Tetsuo Sasaki, Tooru Hiyama, Tatsuki Ishii, Yousuke Nagao, Yasuo Satou, Hisahiro Takeuchi (Hitachi Ltd.) Path Delay Optimization Placement Techniques Tetsuo Sasaki, Tatsuki Ishii, Tooru Hiyama, Yasushi Ogawa, Hachidai Nagase, Yasuo Satou (Hitachi Ltd.) Kiyoshi Endou (Hitachi Software Engineering Co., Ltd.) A Rip up Replace Method for PCB Shinji Miura, Hiroyuki Yoshimura, Hirokazu Uemura, Hideo Aoe (Matsushita Electric Industrial Co., Ltd.) Expert Ststem of Placement for PWB Keiichi Handa, Hiroshi Tsukimoto, Chihiro Horiuchi, Kazuhiro Okumoto (Toshiba Corporation) Knowledge-based Router for PCB Yuichi Nishimura, Hiroyuki Yoshimura, Hirokazu Uemura, Hideo Aoe (Matsushita Electric Industrial Co., Ltd.) A Maze-router on a Vector Processor Yoshio Miki, Kei Suzuki, Yoshio Takamine (Hitachi Ltd.) Commonly-used Computer Address Adder Bypass Logic: A Logic for Minimizing Address Generation Interlock Delay in HITAC M-880 Instruction Processor Tooru Shonai, Yooichi Shintani, Kazunori Kuriyama, Eiki Kamada, Kiyoshi Inoue (Central Research Lab, Hitachi Ltd.) Kooji Nakamura (Kanagawa Works, Hitachi Ltd.) Speed up Method for Storage Operand Conflict Applied to HITAC M-880 Eiki Kamada, Yooichi Shintani, Tooru Shonai, Kiyoshi Inoue, Seiji Nagai (Hitachi Ltd.) Performance Evaluation Method using Logic Simulation for Development of HITAC M-880 Kiyoshi Inoue, Yooichi Shintani (Central Research lab., Hitachi Ltd.) Kanji Kubo, Zentaro Hirose (Kanagawa Works, Hitachi Ltd.) Multiprocessor Performance Evaluation Technique for Main Frame Computer Seiji Kaneko, Yasuhisa Tamura, Akio Yamamoto, Masaya Watanabe, Toshiyuki Kinoshita (Hitachi Ltd.) High Performance Architecture for M-880 Multiprocessor Yasuhisa Tamura, Seiji Kaneko, Akio Yamamoto, Masaya Watanabe, Toshiyuki Kinoshita (Hitachi Ltd.) Implementation of Enhanced Usability for Mainframe Computer with Service Processor Hitoshi Ueno (Hitachi Ltd.) SYSTEM Office System Decision Support System Engine based on SQL Yuji Honda (Oki Electric Industry Co., Ltd.) Design of Enterprise's Internal Mail System Hideyuki Umeoka (Fujitsu Ltd.) An Implementation and Evaluation of PC Document Conference System Toshiaki Tanaka, Kouji Nakao (KDD R&D Laboratories) The Next Generation Integrated Office System - Systems Overview Terumi Sawada, Nobuo Hanada, Kazutaka Tokunaga, Yukio Yamazaki (NEC Corporation) Tne Next Generation Integrated Office System - Adaptation of the Server/Client Model for the Office System Kensaku Tsutsui, Hiroko Suzuki, Seiji Yamasuga (NEC Software Kobe, Ltd.) Kimiaki Kagaya, Masayoshi Atsumi (NEC Corp.) Tne Next Generation Integrated Office System - The Method to Manage the Information on the User's Customization Yoshiko Watanabe (NEC Software Chugoku, Ltd.) Kensaku Tsutsui (NEC Software Kobe, Ltd.) Hiroyuki Shimade (NEC Corporation) Integrated Office System II - Environment for the Construction of Office Applications Hiroshi Wakabayashi, Koji Sugita, Chiharu Kitano (EDP Systems Engineering Division, NEC Corporation) The Next Generation Integrated Office System - The Administration of the Office Information Kazutaka Inoue, Takashi Ishio (NEC Software Chugoku, Ltd.) Masako Sugaya (NEC Corporation) The Next Generation Integrated Office System - Management of the Distributed Server in the Office System Norio Shimizu, Shinya Mikado, Takashi Kawashima (NEC Corporation) Control Systems for use in the Distributed Office System Fumiyoshi Himeno, Hisamitsu Yamamoto (NEC Corporation) CAI User Interface A Method of Inferring in the Intelligent CAI System CAIRNEY and its Evaluations Minoru Kiyama, Yoshimi Fukuhara (NTT Communications and Information Processing Laboratories) Courseware Implementation Method of the Intelligent CAI System CAIRNEY Yoshimi Fukuhara, Osamu Mino (NTT Communications and Information Processing Laboratories) A Method of Using Information on Language Functions for an ICAI System for Training a Foreign Language Katsuya Oba (Osaka Gas Information System Research Institute) Kyoko Kai (Oki Electric Ind. Co., Ltd.) The System Learning Any Subject Taught by User Ikuko Harada, Yoshiyuki Kotani (Tokyo University of Agriculture and Technology) SQL Automatic Generation in Spreadsheet Calculator Hajime Otogao, Hiroyuki Arai, Kazunori Oonishi (Toshiba Ltd.) Data Analysis Function in Graph Yutaka Inaba, Masao Fujihara, Hajime Otogao (Toshiba Ltd.) Case Study of Shared Window System Architecture Eiji Kuwana, Seiichi Komura, Masashi Shibasaki (NTT Software Laboratories) The Performance Evaluation of the Database Macro-functions of Making the Spreadsheet Fukashi Gotoh, Kiyoshi Okamoto, Yuji Wada (Mitsubishi Electric Corp.) Mechanical Design Assistant Shell K. Tahara, T. Kato (Kayaba Industry Co., Ltd.) An Extension of the Winograd's Basic Conversation Diagram to the Case of Three Members Seiichi Komura, Masashi Shibasaki (NTT Software Laboratories) The NaviGlasses: A Media for Realize Artificial Telepathy Shigemitsu Ohzahata (Macintelligence, Inc.) Decentralized System Autonomous Decentralization Concept and Computer System Yasuo Suzuki, Kinji Mori (Systems Development Laboratory, Hitachi Ltd.) Hirokazu Kasashima, Shinji Hori (Omika Works, Hitachi Ltd.) Toshihiko Itou (Industrial & System Dept., Hitachi Ltd.) Operating System for Autonomous Decentralized System and Test Technique Hisao Kikuchi, Katsuo Suzuki (Hitachi Process Computer Engineering, Inc.) Hirokazu Kasashima (Omika Works, Hitachi Ltd.) Kinji Mori (System Development Laboratory, Hitachi Ltd.) Intelligent Communication Processor in Autonomous Decentralized System Shinji Hori, Hirokazu Kasashima (Omika Works, Hitachi Ltd.) Yasuo Suzuki, Kinji Mori (Systems Development Laboratory, Hitachi Ltd.) Hideaki Koike, Shuuichi Sakuyama (Hitachi Engineering Co., Ltd.) An Example of Applying Autonoumous Decentralized System to Iron and Steel Industry Koichi Doi, Nobuharu Sakuma (Hitachi Engineering Co., Ltd.) Shinji Hori (Omika Works, Hitachi Ltd.) Kinji Mori, Yasuo Suzuki (Systems Development Laboratory, Hitachi Ltd.) An Test Method in Autonomous Decentralized System Nobuharu Sakuma, Koichi Doi, Hideaki Koike (Hitachi Engineering Co., Ltd.) Shinji Hori (Omika Works, Hitachi Ltd.) Yasuo Suzuki (Systems Development Laborlatory, Hitachi Ltd.) Autonomous Decentralized Software Design and Programming Support Tsunao Kanzaki (Hitachi Microcomputer System Ltd.) Yasuo Suzuki, Kinji Mori (Systems Development Lab., Hitachi Ltd.) Shinji Hori (Omika Works, Hitachi Ltd.) Kouichi Doi (Hitachi Engineering Co., Ltd.) Autonomous Decentralization System and its Application for Industry Toshihiko Itou (Industrial & System Dept., Hitachi Ltd.) Yasuo Suzuki (Systems Development Laboratory, Hitachi Ltd.) Shinji Hori (Omika Works, Hitachi Ltd.) OZ+: Object Oriented Open Distributed System - Extension of OZ+ Communication Architecture Michiharu Tukamoto (Electrotechnical Laboratory) Isao Mizutani (Sumitomo Electric Industries, Ltd.) Hiroyuki Kaziura (Sharp Corporation) Hiroki Shinohara (Matsushita Electric Industrial Co., Ltd.) OZ+: Object Oriented Open Distributed System - Multicast RPC for OZ+ Michiharu Tukamoto (Electrotechnical Laboratory) Hiroyuki Kaziura (Sharp Corporation) Isao Mizutani (Sumitomo Electric Industries, Ltd.) Hiroki Shinohara (Matsushita Electric Industrial Co., Ltd.) OZ+: Object orented Oepn Distributed System - A Version Function in OZ+ Michiharu Tukamoto (Electrotechnical Laboratory) Hiroki Shinohara (Matsushita Electric Industrial Co., Ltd.) Isao Mizutani (Sumitomo Electric Industries, Ltd.) Hiroyuki Kaziura (Sharp Corporation) CAD A Discussion on the Knowledge-base for Mechanical Designs based on the Hierarchy of the Mechanical Structure Masaki Yoneyama, Yoshiharu Takeda, Hiroaki Kobayashi, Tadao Nakamura (Tohoku University) Development of a Reactor Vessel Design System (1) Toshihiko Mochizuki, Takashi Tutida (Toshiba Case Systems Incorp.) Sigeru Kisi, Satosi Ohte (Toshiba Corp.) A Meta-model for a CAD Database and its Visual Environment Deepa Krishnan, Tosiyasu L. Kunii (The University of Tokyo) Stabilization of Grid Attraction for Boundary-Fitting Method: FEM Analysis Supporting System WING (11) Hiroyasu Enomoto (Yokohama Research Laboratory Babcock-Hitachi K.K.) Masahiro Shimazu (Bab Hitachi East Software Co., Ltd.) Bus Scheduling System Masamoto Kashiwagi, Kiyoshi Muto, Hajime Yano (Toshiba Corp.) CIM Production Parameter Driven Scheduler Mariko Hashimoto, Shusuke Nakayama, Mariko Yamamoto, Toshiharu Aoki, Jyunichirou Tanaka (NEC Co.) Masami Tunekazu (NEC Scientific Information System Development, Ltd.) On Invariant Set of Production System Represented by Petri Net Hiroyuki Yamada, Yoshio Sugasawa, Sugayasu Hirano (Nihon University) The Fundamental System Concept for Micro-scheduling - The Study on Scheduling for Logistic Production by Timed Petri Net Takumi Kojima (Tokyo Institute of Japan Small Business Corporation) Shinichi Osawa (INES Corporation) Yoshio Sugasawa (Nihon University) Utilizing Error Cancellation in Parallel Assembly Kaoru Maeda, Tosiyasu L. Kuni (Department of Information Science, The University of Tokyo) The Designing Process and Structure Function of Logical Structure in Sensor-base Network Systems Toshio Takahara, Hiroto Shingai, Kaori Suzuki (Fujitsu Network Engineering Ltd.) Behavior Analysis of Trap Systems Using Stochastic Petri Nets Qun Jin, Yoshio Sugasawa, Koichiro Seya (Nihon University) Research for Distributed CIM with Workstations and Database Koji Doi (OMRON Co. Intelligent Controller Laboratory) Operation Design for CIM Masaaki Kaneko (Fujitsu Ltd.) --------------END OF REPORT (BOOK 6)----------------------------------------