Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!stanford.edu!agate!sunspot.berkeley.edu!johnf From: johnf@ssl.berkeley.edu (John Flanagan) Newsgroups: comp.sys.amiga.hardware Subject: Re: How does an expansion board control DTACK*? Message-ID: Date: 7 May 91 23:33:16 GMT References: <21304@cbmvax.commodore.com> Sender: root@agate.berkeley.edu (Charlie Root) Organization: CEA @ UC Berkeley, Berkeley, CA, USA. Lines: 23 In-Reply-To: daveh@cbmvax.commodore.com's message of 6 May 91 21: 09:50 GMT In article <21304@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes: [Lots of useful information. Thanks!] Actually, I've just realized that since GARY presumably generates the same DTACK* timings regardless of processor speed (since it is clocked at the motherboard's 7.14 MHz), my problem can't be with the hardware but rather with the software; the interface does work at slower CPU speeds. I'll have to try adding some delays, or readiness polling, to the device driver's data transfer loops, whenever my registration package arrives. I hope the registration package does contain the source code. Thank you, Dave. John -- John Flanagan Center for EUV Astrophysics johnf@ssl.berkeley.edu University of California (...!ucbvax!soc1.ssl!johnf) Berkeley, CA 94720