Path: utzoo!utgpu!news-server.csri.toronto.edu!torsqnt!lethe!yunexus!rreiner
From: rreiner@yunexus.YorkU.CA (Richard Reiner)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: IRQ 2 on AT-class machines
Message-ID: <22648@yunexus.YorkU.CA>
Date: 5 May 91 15:16:08 GMT
Article-I.D.: yunexus.22648
References: <160@thor.sdrc.com> <3WC+R0F@jwt.UUCP> <li.673350356@mrcnext.cso.uiuc.edu> <H=D++AH@jwt.UUCP> <li.673438213@mrcnext.cso.uiuc.edu>
Organization: York U. Computing Services
Lines: 14

li@mrcnext.cso.uiuc.edu (hans li) writes:

>nope, irq 2 is used for the cascade interrupt, usually if you're running
>MULTIPLE controllers.

Look here: several of us have disputed this claim, and asked you for
evidence.  Merely repeating your apparently erroneous assertion is bad
manners.

From what you say this time, I think I see what your confusion is: the
cascade interrupt is between the two PICs (the interrupt controllers),
not between hd controllers.

//richard