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Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hplabs!pyramid!jetsun!paulc
From: paulc@jetsun.weitek.COM (Paul Chai)
Newsgroups: comp.dcom.lans,comp.sys.novell
Subject: HELP !!! needed on ethernet driver s/w
Message-ID: <1991May8.165555.16300@jetsun.weitek.COM>
Date: 8 May 91 16:55:55 GMT
References: <6843@s3.ireq.hydro.qc.ca> <1991May7.233920.7888@engin.umich.edu> <1991May8.030725.3387@netcom.COM>
Reply-To: paulc@jetsun.WEITEK.COM (Paul Chai)
Organization: WEITEK, Sunnyvale CA
Lines: 18

If there are any kind souls out there fluent in ethernet s/w drivers
in particular with the AMD LANCE chip, i need help with the following
questions??? Any help would be highly appreciated!!
Questions:
 1. Is it reasonable/doable to insist memory buffers start on a quadword/word
    address rather than any arbitrary byte address??? The receive/transmit
    descriptor rings are after all on quadword address boundary.
 2. ON ethernet Read/Write DMA transfers, you have the following data
    pattern "....,addr,data,addr,data,.....,addr,data" . Is it safe to assume
    in a contiguous transfer ie. HOLD- continously asserted that all the
    addresses are consecutive eg. 10,12,14,16,...etc??? This would enable
    one to only need to buffer the first address.
 3. What is the appropriate way of draining data to memory during a DMA
    write transfer??? Wait for a Lance interrupt to do it ???

thank you all....

paulc