Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!sdd.hp.com!uakari.primate.wisc.edu!caen!ox.com!math.fu-berlin.de!uniol!unido!rwthinf!slcdec!hippo!f1.n6000.z2.fidonet.org!f24.n116.z1.fidonet.org!Kevin_Zelhart From: Kevin_Zelhart@f24.n116.z1.fidonet.org (Kevin Zelhart) Newsgroups: comp.windows.ms.programmer Subject: 486sx Message-ID: Date: 1 May 91 05:45:43 GMT Reply-To: Kevin_Zelhart%f24.n116.z1@hippo.dfv.rwth-aachen.de (Kevin Zelhart) Organization: EET BBS @ Nashville Tech (615) 353-3476 Lines: 5 Comment-To: Joachim_Kainz@f1.n6000.z2.fidonet.org (Joachim Kainz) I haven't seen any serious documentation on it yet, but I imagine they have done their typical routine of cutting the bus width in half while still maintaining the main processor structure. If I see any blurbs in EE times, I'll *post them. KMZ