Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uwm.edu!linac!att!att!andante!alice!jmk
From: jmk@alice.att.com (Jim McKie)
Newsgroups: comp.arch
Subject: Re: Clarification on 3 Addr vs 2 Addr Archs
Message-ID: <20334@alice.att.com>
Date: 9 May 91 17:55:47 GMT
Organization: AT&T Bell Laboratories, Murray Hill NJ
Lines: 22


In response to <673707950@romeo.cs.duke.edu>:
	I once proposed an architecture that featured "2.5" addresses, instead of the
	usual 2 or 3.  Each instruction contains two complete register numbers, call
	them A and B, as in a conventional 2-address machine, plus one extra bit
	which indicated whether the third address (the destination) should be the
	same as A or should be register zero (the accumulator).
	...
	This was only an idea, and was never tested.  I would be interested to hear
	if John Van Zandt, or anyone else, has ever looked at this addressing scheme
	and what they found after looking at it for a while.

See 'Introduction to the CRISP Instruction Set Architecture',
Spring COMPCON 87 Proceedings, by Berenbaum, Ditzel and McLellan
for a description of a 2.5 address machine:

	"An accumulator rather than a full third address was provided because
	our measurements showed that most of the use of a full third address
	destination field by the compiler was for a single scratch register."

Jim McKie	research!jmk	-or-	jmk@research.att.com
Bell Labs