Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!uunet!munnari.oz.au!mel.dit.csiro.au!yarra!bohra.cpg.oz.au!als From: als@bohra.cpg.oz.au (Anthony Shipman) Newsgroups: comp.arch Subject: Re: Memory speed, why so slow? Summary: multiplexing changes? Message-ID: <1991May10.035511.29155@bohra.cpg.oz.au> Date: 10 May 91 03:55:11 GMT References: <9245@idunno.Princeton.EDU> Organization: Software Division, Computer Power Group Lines: 56 In article , raje@lattice.stanford.edu (Prasad Raje) writes: > > In article <9245@idunno.Princeton.EDU> ssr@stokes.Princeton.EDU (Steve S. Roy) > asks: > Is it my imagination or is it true that while the storage capacity of > dynamic RAM chips has increased by orders of magnitude the speed has > not? ................. > > Speed: > Very roughly > Memory access time = time spent in the decoders (1) > + time spent to drive the word line (2) > + time the dinky cell takes to drive the bit line (3) > + time taken for column select and sensing (4) > + other misc stuff before your bit is on the pins (5) > > (1) decreases with each technology generation (faster transistors) but > increases because there is more decoding to be done in the larger DRAM > (2) decreases because of faster transistors but increases because word lines > get longer because of the larger RAM array (remember chip areas are increasing) > (3) DRAM cell designers kill themselves to keep cell capacitance constant. > (see above) Bit line capacitance is increasing because of the larger array. > Overall, there is a slight increase. > (4) same as (1) > (5) constant > > The result? Total delay is constant. ................ > There are however some innovations coming around. Some that I like > personally > > 1. Cache DRAMs: DRAMs with an on chip SRAM cache[1]. This looks to the > outside world as a large memory (say 4Mbit) with an SRAM like average > access time (say 10ns). > > 2. BiCMOS DRAMs: allows one to further decrease delays (1),(2),(4),(5) > by using bipolar transistors. The down side is the added process complexity. > > If the market demands it (ie pays for it) I would say we can have a research > prototype of a 16Mbit 5ns BiCMOS cache DRAM today. (you may realize I have > my fantasy hat on) > > Prasad I read a while back that one improvement being considered for large dynamic RAMS was removing the multiplexing of the row and column addresses, saving some time. Is this still on the cards? -- Anthony Shipman "You've got to be taught before it's too late, Computer Power Group Before you are six or seven or eight, 19 Cato St., East Hawthorn, To hate all the people your relatives hate, Melbourne, Australia You've got to be carefully taught." R&H