Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!sdd.hp.com!wuarchive!uunet!stanford.edu!cascade.stanford.edu!cascade!raje From: raje@lattice.stanford.edu (Prasad Raje) Newsgroups: comp.arch Subject: Re: Memory speed, why so slow? Message-ID: Date: 10 May 91 15:02:43 GMT References: <9245@idunno.Princeton.EDU> <1991May10.035511.29155@bohra.cpg.oz.au> Sender: news@cascade.Stanford.EDU (USENET News System) Organization: Center for Integrated Systems, Stanford Lines: 26 In-Reply-To: als@bohra.cpg.oz.au's message of 10 May 91 03:55:11 GMT In article <1991May10.035511.29155@bohra.cpg.oz.au> als@bohra.cpg.oz.au (Anthony Shipman) writes: I read a while back that one improvement being considered for large dynamic RAMS was removing the multiplexing of the row and column addresses, saving some time. Is this still on the cards? Having separate column addr pins wont buy a whole lot. This is because the inherent signal flow in a DRAM access has a lag between the time that you present the row addr and the time that you need the column addr for the column select. That is, the row decoding, word line driving, bit line swinging all take up time before you can do anything useful with the column address. Now if extra pins were available, what I would use them for is extra data lines. In general, the memory array is partitioned so that as many 1024 bits are available (inside the chip) after a single row access - sensed and all ready to go. Then along comes the column decode that selects one of these bits for the output. Obviously shipping 1024 bits out would be tough, but it seems like a waste to ship out just one. 16 or 32 seems like a reasonable number and this would dramatically increase the bandwidth of the DRAM. (the current compromise for this is page mode, static column mode, nibble mode etc.) Prasad