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From: ex2mike@cybaswan.UUCP ( m overton)
Newsgroups: comp.arch
Subject: Re: endian etc
Keywords: endianness??, cache
Message-ID: <2496@cybaswan.UUCP>
Date: 10 May 91 22:38:37 GMT
Lines: 18


A simple answer to all the problems with byte order etc, to the
authors mind, is to have a duplicate set of load and store instructions.
Since most RISC machines have very few of them, adding a set for the
opposite sense would surely be very easy. It wouldn't work with 
instructions, of course, but I assume that is not a problem. 

On a completely different subject, there has been a number of articles
recently on the subject of caches. One of my particular ideas on these
is as follows...

	Wouldn't it be very easy on a machine with a write back cache
to copy words simply by changing the internal cached address ( a little
like a form of cache aliasing). A lot of time is spent in most code
just copying things around. Would this not improve things ( you gain
immediately on cache occupancy).

Mike Overton - ex2mike@pyr.swan.ac.uk