Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!unix.cis.pitt.edu!dsinc!ub!uhura.cc.rochester.edu!rochester!pt.cs.cmu.edu!gandalf.cs.cmu.edu!lindsay From: lindsay@gandalf.cs.cmu.edu (Donald Lindsay) Newsgroups: comp.arch Subject: Re: RISC vs. CISC -- SPECmarks Keywords: Signetics VLIW Message-ID: <13010@pt.cs.cmu.edu> Date: 12 May 91 05:00:25 GMT References: <1991May7.195913.27363@riacs.edu> Organization: Carnegie Mellon Lines: 9 In article <1991May7.195913.27363@riacs.edu> lamaster@pioneer.arc.nasa.gov (Hugh LaMaster) writes: >Someone ought to be working on a single chip VLIW, if they aren't >already. But, I haven't heard of anyone. In many ways, VLIW seems to be >a simpler and more general form of "vectorization". As of a year ago, Philips/Signetics had a VLIW chip. -- Don D.C.Lindsay Carnegie Mellon Robotics Institute