Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!rice!ariel.rice.edu!preston
From: preston@ariel.rice.edu (Preston Briggs)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991May13.144955.21618@rice.edu>
Date: 13 May 91 14:49:55 GMT
References: <1991Apr22.044553.16805@mp.cs.niu.edu> <1991Apr27.012655.6508@rice.edu> <_R9B1S2@xds13.ferranti.com>
Sender: news@rice.edu (News)
Organization: Rice University, Houston
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peter@ficc.ferranti.com (peter da silva) writes:
>>>Ah, the old Von Neumann botleneck. Time to apply RISC design techniques to
>>>memory subsystems.

and I (obscurely) wrote
>> Well, you _could_ rediscover the Connection Machine.

and he replies
>Is it reasonable to think about scaling the CM down to a desktop workstation?

Probably not.  However, ...
Very early in his thesis, Hillis makes some interesting points.
He notices that the number of transistors in large computers is becoming
huge.  However, only those in the CPU are heavily employed.
The bulk of the memory sits idle most of the time.  He also notes
that most of our efforts have been devoted to keeping the
CPU "wonderfully busy."  This leads him to consider a machine with a
better balance between CPU and memory: the CM.

I usually cuss the bottleneck because I'm having trouble keeping
the CPU 100% busy.  Hillis' point makes more economic sense.

Preston Briggs