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From: daryl@hpcupt3.cup.hp.com (Daryl Odnert)
Newsgroups: comp.arch
Subject: Re: Scalar vs Superscalar
Message-ID: <45760016@hpcupt3.cup.hp.com>
Date: 10 May 91 22:38:59 GMT
References: <1991May6.152803.5886@midway.uchicago.edu>
Organization: Hewlett Packard, Cupertino
Lines: 40

> I have often heard the HP snake machines described as "not superscalar"
> whereas the IBM RS/6000 are generally described as "superscalar."
> What is it in the architectures of these two machines that supports
> this distinction?

First, one must be careful to distinguish between "architecture" and
"implementation".  "Architecture" is what the complier or assembly code
writer must adhere to for correct execution of a program.  "Implementation"
is a particular instantiation of an architecture.

There is nothing in the PA-RISC architecture which prevents a superscalar
implementation from being built.  However, the processor in the Snakes
workstations issues only one instruction per clock cycle to either the
CPU or the FPU and therefore it is not considered a superscalar implementation.

If my understanding of the IBM architecture is correct, there is nothing
which *requires* an RS/6000 implementation to be superscalar.


> 		    What are the consequences for the kinds of codes
> that will run efficiently (particularly in terms of floating point
> performance)?

Consider the following equation:

    CPU Seconds      Instructions    Avg Cycles     Seconds
    -----------  =   ------------ *  ----------- * ---------
    Application      Application     Instruction     Cycle

The main consequence (or objective) of a superscalar implementation
is to significantly reduce the average cycles-per-instruction.  This
tends to work quite well on floating-point applications.  Thus, the RS/6000
is able to achieve a floating-point SPEC ratio of >50 with a 20 MHz processor,
while the HP Series 700 achieves a floating-point SPEC ratio of >70 with a
50 MHz processor.  So, the IBM machine achieves about 2.5 floating-point
SPECmarks per MHz, while the HP machine achieves about 1.4.

Daryl Odnert      daryl@hpclopt.cup.hp.com
Hewlett-Packard
California Language Lab